SLUSFL6C November   2024  – June 2025 TPSM82866C

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Options
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Save Mode
      2. 7.3.2 Forced PWM Mode
      3. 7.3.3 Optimized Transient Performance from PWM to PSM Operation
      4. 7.3.4 Low Dropout Operation (100% Duty Cycle)
      5. 7.3.5 Enable and Soft-Start Ramp
      6. 7.3.6 Switch Current Limit and HICCUP Short-Circuit Protection
      7. 7.3.7 Undervoltage Lockout
      8. 7.3.8 Thermal Warning and Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Enable and Disable (EN)
      2. 7.4.2 Start-Up Output Voltage and I2C Target Address Selection (VSET)
      3. 7.4.3 Select Output Voltage Registers (VID)
      4. 7.4.4 Output Discharge
      5. 7.4.5 Power Good (PG)
    5. 7.5 Programming
      1. 7.5.1 Serial Interface Description
      2. 7.5.2 Standard-Mode, Fast-Mode, and Fast-Mode Plus Protocol
      3. 7.5.3 HS-Mode Protocol
      4. 7.5.4 I2C Update Sequence
      5. 7.5.5 I2C Register Reset
  9. 8 Register Map
    1. 8.1 Target Address Byte
    2. 8.2 Register Address Byte
    3. 8.3 VOUT Register 1
    4. 8.4 VOUT Register 2
    5. 8.5 CONTROL Register
    6. 8.6 STATUS Register
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input and Output Capacitor Selection
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
        1. 9.4.2.1 Thermal Considerations
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

6.5 Electrical Characteristics

TJ = –40°C to 125°C, and VIN = 2.4V to 5.5V. Typical values are at TJ = 25°C and VIN = 5V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
IQ_VIN Quiescent current into VIN pin EN = High, no load, device not switching 4 10 µA
IQ_VOS Quiescent current into VOS pin EN = High, no load, device not switching, VVOS = 1.8V 18 µA
ISD Shutdown current(1) EN = Low, TJ = –40℃ to 85℃
 0.24 1 µA
VUVLO Undervoltage lockout threshold VIN rising 2.2 2.3 2.4 V
VIN falling 2.1 2.2 2.3 V
TJW Thermal warning threshold TJ rising 130 °C
Thermal warning hysteresis TJ falling 20 °C
TJSD Thermal shutdown threshold TJ rising 150 °C
Thermal shutdown hysteresis TJ falling 20 °C
LOGIC INTERFACE
VIH High-level input threshold voltage at EN, SCL, SDA and VSET/VID 0.84 V
VIL Low-level input threshold voltage at EN, SCL, SDA and VSET/VID 0.4 V
ISCL,LKG Input leakage current into SCL pin 0.01 0.8 µA
ISDA,LKG Input leakage current into SDA pin 0.01 0.1 µA
IEN,LKG Input leakage current into EN pin 0.01 0.1 µA
CSCL Parasitic capacitance at SCL 1 pF
CSDA Parasitic capacitance at SDA 2.4 pF
START-UP, POWER GOOD
tDelay Enable delay time Time from EN high to device starts switching with a 249kΩ resistor connected between VSET/VID and GND 420 650 1100 µs
VPG(low) Power-good lower threshold VOUT referenced to VOUT(nominal) 85 91 96 %
VPG(high) Power-good upper threshold VOUT referenced to VOUT(nominal) 103 111 120 %
VPG,OH High-level output voltage Vin V
tPG,DLY Power-good delay Rising and falling edges 34 µs
OUTPUT
VOUT Output voltage accuracy FPWM, no Load, TJ = 0℃ to 85℃ –1 1 %
FPWM, no Load –2 2 %
IVOS,LKG Input leakage current into VOS pin EN = Low, Output discharge disabled, VVOS = 1.8V 0.2 2.5 µA
RDIS Output discharge resistor at VOS pin 3.5 Ω
Load regulation VOUT = 0.9V, FPWM  0.04 %/A
POWER SWITCH
RDP
Dropout resistance

 100% mode. VIN = 3.3V, TJ = 25°C 26 mΩ
ILIM High-side FET forward current limit TPSM82864xx 5 5.5 6 A
TPSM82866xx 7 7.9 9 A
Low-side FET forward current limit TPSM82864xx 4.5 A
TPSM82866xx 6.5 A
Low-side FET negative current limit –3 A
fSW PWM switching frequency IOUT = 1A, VOUT = 0.9V 2.4 MHz
(1) Does not include the current out of the VSET/PG pin.  See Power Good (PG).