SLUUC44A July   2019  – December 2022 TPSM82810 , TPSM82813 , TPSM82816

 

  1.   TPSM8281xEVM-089 Evaluation Module
  2.   Trademarks
  3. 1Introduction
    1. 1.1 Performance Specification
    2. 1.2 Modifications
      1. 1.2.1 Input and Output Capacitors
      2. 1.2.2 Switching Frequency, Spread Spectrum and Control Loop Compensation
      3. 1.2.3 Soft-Start Time
      4. 1.2.4 Loop Response Measurement
      5. 1.2.5 Precise Turn-on Voltage
  4. 2Setup
    1. 2.1 Hardware Setup
    2. 2.2 Input, Output Connector, and Jumper Descriptions
  5. 3Safety Instructions
  6. 4TPSM8281xEVM-089 Test Results
  7. 5Board Layout
  8. 6Schematic and Bill of Materials
    1. 6.1 Schematic
    2. 6.2 Bill of Materials
  9.   A Appendix - Rev.A EVM
    1.     A.1 Rev.A - Setup
      1.      A.1.1 Rev.A - Connector Descriptions
      2.      A.1.2 Rev.A - Hardware Setup
    2.     A.2 Rev.A - Board Layout
    3.     A.3 Rev.A - Schematic and Bill of Materials
      1.      A.3.1 Rev.A - Schematic
      2.      A.3.2 Rev.A - Bill of Materials
  10.   B Revision History

A.1.1 Rev.A - Connector Descriptions

    J1, Pin 1 and 2 – VINPositive input voltage connection from the input supply for the EVM
    J1, Pin 3 and 4 – S+/S–Input voltage sense connections; measure the input voltage at this point.
    J1, Pin 5 and 6 – GNDInput return connection from the input supply for the EVM
    J2, Pin 1 and 2 – VOUTPositive output voltage connection
    J2, Pin 3 and 4 – S+/S–Output voltage sense connections; measure the output voltage at this point.
    J2, Pin 5 and 6 – GNDOutput return connection
    JP1 – ENEN pin jumper. Place the supplied jumper across ON and EN to turn on the IC. Place the jumper across OFF and EN to turn off the IC.
    JP2 – MODE/SYNCMODE/SYNC pin jumper. Place the supplied jumper across VIN and MODE/SYNC to force the device in fixed frequency PWM operation at all load currents. Place the jumper across MODE/SYNC and GND to enable power save mode. Connect a clock signal to MODE/SYNC referenced to GND to synchronize the switching frequency to the clock signal.
    JP3 – COMP/FSETDevice compensation and frequency set input. When the jumper is open, the resistor R4 from this pin to ground defines the compensation of the control loop as well as the switching frequency if it is not externally synchronized. The COMP/FSET pin connects pin 1 and 2 and is tied to VIN. Comp setting 1 (for smallest output capacitance) is set and the switching frequency is internally fixed at 2.25 MHz. The COMP/FSET pin connects pin 2 and 3 and is tied to GND. Comp setting 3 (for large output capacitance) is set and the switching frequency is internally fixed at 2.25 MHz.
    JP4 – SS/TRSS/TR input. A voltage connected on pin 1 of this header referenced to GND on pin 2 can be used to control the output voltage (tracking). Change the capacitor from SS/TR pin to GND to adjust the soft-start ramp time.
    JP5 – PGThe PG output appears on pin 1 of this header with a convenient ground on pin 2.