SLUUC68A August   2020  – April 2021 TPS563207


  1.   Trademarks
  2. 1Introduction
  3. 2Performance Specification Summary
  4. 3Modifications
    1. 3.1 Output Voltage Setpoint
  5. 4Test Setup and Results
    1. 4.1 Input/Output Connections
    2. 4.2 Start-Up Procedure
    3. 4.3 Start-Up
    4. 4.4 Shut-Down
    5. 4.5 Output Voltage Ripple
    6. 4.6 Input Voltage Ripple
    7. 4.7 Load Transient Response
  6. 5Board Layout
    1. 5.1 Layout
  7. 6Schematic, Bill of Materials, and Reference
    1. 6.1 Schematic
    2. 6.2 Bill of Materials
    3. 6.3 Reference
  8. 7Revision History


The board layout for the TPS563207EVM is shown in Figure 5-1, Figure 5-2, and Figure 5-3. The top layer contains the main power traces for VIN, VOUT, and ground. The top layer also has the connections for the pins of the TPS563207 and a large area filled with ground. Most of the signal traces are also located on the top side. The input decoupling capacitors, C2, C3, and C4 are located as close to the IC as possible. The input and output connectors, test points, and all of the components are located on the top side. The bottom layer is a ground plane along with the switching node copper fill, signal ground copper fill and the feed back trace from the point of regulation to the top of the resistor divider network. Both the top layer and bottom layer use 2-oz. copper thickness.

Figure 5-4 and Figure 5-5 are the TPS563207EVM top view and bottom view, respectively.

GUID-20200816-CA0I-RWKW-S0NW-62GZVL4XX31J-low.jpg Figure 5-1 TPS563207EVM Top Assembly
GUID-20200816-CA0I-GGJM-M8P7-0HRVCPQNWN9M-low.jpg Figure 5-2 TPS563207EVM Top Layer
GUID-20200816-CA0I-FZM4-R9ML-VVSQ8NVDQ2LR-low.jpg Figure 5-3 TPS563207EVM Bottom Layer
GUID-20200823-CA0I-XRNZ-S9G6-FP9HVW88SBTL-low.jpg Figure 5-4 TPS563207EVM Board Top View
GUID-20200816-CA0I-638F-8WL8-QKWPN2GWNZDJ-low.jpg Figure 5-5 TPS563207EVM Board Bottom View