SLUUCJ2C july   2021  – august 2023 UCC14240-Q1 , UCC14241-Q1 , UCC15240-Q1 , UCC15241-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 U1 Component Selection
    2. 1.2 Pin Configuration and Functions
  5. 2Description
    1. 2.1 EVM Electrical Performance Specifications
  6. 3Schematic
  7. 4EVM Setup and Operation
    1. 4.1 Recommended Test Equipment
    2. 4.2 External Connections for Easy Evaluation
    3. 4.3 Powering the EVM
      1. 4.3.1 Power on for Start-up
      2. 4.3.2 Power off for Shutdown
    4. 4.4 EVM Test Points
    5. 4.5 Probing the EVM
  8. 5 Performance Data
    1. 5.1  Efficiency Data
    2. 5.2  Regulation Data
    3. 5.3  Steady State Input Current
    4. 5.4  Start-up Waveforms
    5. 5.5  Inrush Current
    6. 5.6  AC Ripple Voltage
    7. 5.7  EN-to-/PG Timing
    8. 5.8  RLIM
    9. 5.9  Fault Protection
      1. 5.9.1 Output UVLO
      2. 5.9.2 Output OVP
    10. 5.10 Shutdown
    11. 5.11 Thermal Performance
  9. 6Assembly and Printed Circuit Board (PCB) Layers
  10. 7Bill of Materials (BOM)
  11. 8Revision History

2.1 EVM Electrical Performance Specifications

Table 2-1 EVM Electrical Specifications VIN = 24 V, VDD=VDD-VEE = 20 V, VEE=VEE-COM = 5 V, TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT CHARACTERISTICS
VIN Input voltage range 21 24 27 V
VIN_ON Input voltage on 19 21 V
VIN_OFF Input voltage off 17.1 18.9 V
IIN_FL Input current at full load VIN = 21 V, IVDD = 80 mA 130 mA
VIN = 24 V, IVDD = 80 mA 120
VIN = 27 V, IVDD = 80 mA 115
IIN_NL Input current at no load VIN = 21 V, IVDD =IVEE = 0 mA 14 mA
VIN = 24 V, IVDD =IVEE = 0 mA 13
VIN = 27 V, IVDD =IVEE = 0 mA 12
IIN_OFF Input current at EN LOW EN LOW, VDD = VEE = 0 V 550 650 µA
EN to /PG delay IVDD =IVEE = 0 mA 4 5 ms
OUTPUT CHARACTERISTICS
VDD-VEE DC full load set-point 21 V<VIN<27 V, IVDD = 80 mA 19.92 19.94 19.96 V
IVDD VDD load current range 21 V < VIN < 27 V 0 80 mA
VDD%LD Load regulation V D D R E G = V I ( m i n ) - V I ( m a x ) V I ( m a x ) × 100 %

VIN=24 V, 0 mA ≤ IVDD ≤ 80 mA

 0.336 %
VDD%LN Line regulation V D D R E G = V I ( m i n ) - V I ( m a x ) V I ( m a x ) × 100 %

IVDD=80 mA, 21 V ≤ VIN ≤ 27 V

 0.061 %
VDDAC pk-to-pk AC ripple IVDD = 80 mA 300 350 mV
VDDSS Soft-start IVDD = IVEE = 0 mA 1.8 ms
PMAX Maximum output power IVDD = 100 mA, IVEE = 10 mA 1.5 2 W
VEE-COM DC full load set-point 21 V ≤ VIN ≤ 27 V, IVEE = 10 mA -5.004 -5.007 V
IVEE VEE load current range 21 V≤ VIN ≤ 27 V 0 12 mA
VEEAC pk-to-pk AC ripple IVEE = 10 mA 110 130 mV
SYSTEM CHARACTERISTICS
η100% Full load efficiency IVDD = 80 mA 56 %
η50% Half load efficiency IVDD = 40 mA 53 %
FSW Switching frequency (1) VIN = 21 V, 0 mA < IVDD < 80 mA 16 MHz
VIN = 24 V, 0 mA < IVDD < 80 mA 13
VIN = 27 V, 0 mA < IVDD < 80 mA 27
VDD(OCL) VDD overcurrent limit IVDD > 80 mA 130 145 mA
VEE(OCL) VEE overcurrent limit IVEE > 10 mA 13 15 mA
TMAX Maximum temperature rise above ambient IVDD = 80 mA, IVEE = 10 mA 36 40 °C
(1) Switching frequency is specified as primary-side switching frequency. Secondary-side is 2x primary