SLUUCZ7 August   2025

 

  1.   1
  2.   Description
  3.   Features
  4.   Applications
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  7. 2Hardware
    1. 2.1 Input and Output Connections
  8. 3Implementation Results
    1. 3.1 Test Setup and Results
      1. 3.1.1 Start-Up Procedure
      2. 3.1.2 Load Transient Response
      3. 3.1.3 Start-Up
      4. 3.1.4 Shutdown
      5. 3.1.5 Output Voltage Ripple
    2. 3.2 Output Voltage Setpoint
  9. 4Hardware Design Files
    1. 4.1 Schematic
    2. 4.2 Layout
    3. 4.3 Bill of Materials
  10. 5Additional Information
    1. 5.1 Trademarks
  11. 6References

4.2 Layout

Figure 4-2, Figure 4-3, and Figure 4-4 show the board layout for the TPS543021EVM. The top layer contains the main power traces for VIN, VOUT, and ground. Connections for the pins of the TPS543021 and a large area filled with ground are also on the top layer. Most of the signal traces are also located on the top side. The input decoupling capacitors C2, C3, and C4 are located as close to the IC as possible. The input and output connectors, test points, and all of the components are located on the top side. The bottom layer is a ground plane along with the signal ground copper fill and the feedback trace from the point of regulation to the top of the resistor divider network. Both the top layer and bottom layer use 2-oz copper thickness.

TPS543021EVM TPS543021EVM Top AssemblyFigure 4-2 TPS543021EVM Top Assembly
TPS543021EVM TPS543021EVM Top LayerFigure 4-3 TPS543021EVM Top Layer
TPS543021EVM TPS543021EVM Bottom LayerFigure 4-4 TPS543021EVM Bottom Layer