5 Typical Performance and Waveforms

The application circuit shown in Figure 5-1 is used to generate the data presented in Figure 5-2 – Figure 5-7. The output capacitor used is a 10-µF, 6.3-V, 0603, X5R ceramic capacitor. For a 5-V output, loss of capacitance from the DC bias effect can be significant. Unless otherwise specified, V_IN = 5 V and V_OUT = –5 V.

Figure 5-1 Schematic of the Tested Circuit

Figure 5-2 Efficiency versus Load Current with V_OUT = –5 V

Figure 5-3 Line Regulation with V_OUT = –5 V and 25-mA Load

Figure 5-4 Load Regulation with V_OUT = –5 V

Figure 5-5 Load Transient Response 0 mA to 50 mA with V_IN = 5 V

Figure 5-6 Input Voltage Ripple, V_IN = 5 V and I_OUT = 50 mA

Figure 5-7 Output Voltage Ripple, V_IN = 5 V and I_OUT = 50 mA