SLVA833D October   2016  – May 2021 TPS2660 , TPS2662 , TPS2663

 

  1.   Trademarks
  2. 1 Surge Test (IEC 61000-4-5)
  3. 2 EFuse Solution for Surge Protection
  4. 3 EFuse Solution Schematic for Surge Protection
  5. 4 Circuit Performance for Surge Tests
  6. 5 EFT Test (IEC 61000-4-4)
  7. 6 EFuse Solution Schematic for EFT protection
  8. 7 Circuit Performance for EFT Tests
  9. 8 Power-Fail Test (IEC 61000-4-29)
  10. 9 EFuse Solution Schematic for Power-Fail Applications
  11. 10Circuit Performance for Power-Fail Tests
  12. 11EFT, Surge and Power-Fail Test Setup
  13. 12Conclusion
  14. 13References
  15. 14Revision History

2 EFuse Solution for Surge Protection

GUID-12649176-FC82-4003-8754-A9C58E0B5490-low.gifFigure 2-1 EFuse Integrated Solution

The eFuse-based surge protection solution is shown in Figure 2-1. It requires only a single TVS diode to protect the PLC from surges. The device does not need any passive wave shaping circuits to reduce slew rate of the surge. It can handle slew rates as fast as 20 V/µs. Built-in back-to-back FETs and reverse polarity protection circuits effectively block negative voltage that can be generated due to a negative surge.

The ±70 V transient absolute maximum ratings of the device enables the use of a single TVS diode for clamping the surge. Overvoltage and undervoltage protection makes sure that the downstream converters are isolated from input when the surge is at peak or valley level. A proprietary high-speed protection algorithm immediately disconnects the output from the input and prevents the surge passing from the input to the output.