SLVAFI8 February   2023 TLC6C5748-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2Design Considerations for Low EMI
    1. 2.1 Design Considerations Overview
    2. 2.2 Considerations in Detail
      1. 2.2.1 Top-Level Architecture
      2. 2.2.2 High Frequency Signals
        1. 2.2.2.1  Original Setup
        2. 2.2.2.2  3.3 V I/O Voltage Instead of 5 V
        3. 2.2.2.3  Use Independent OSC for GSCLK With Spread Spectrum
        4. 2.2.2.4  Without Using Buffer on GSCLK
        5. 2.2.2.5  Using Snubber on GSCLK
        6. 2.2.2.6  Lower the Signal Frequency
        7. 2.2.2.7  Placement and PCB layout
        8. 2.2.2.8  ESD Enhancement
        9. 2.2.2.9  Demo and Test Results
        10. 2.2.2.10 Bench Test Results
  5. 3Summary
  6. 4References

2.2.2.7 Placement and PCB layout

As shared previously, R-C or FB-C filters can be used to dump the high frequency harmonics. The recommendation is to place the R-C filters on the system board. Another filter on LED board is also recommended to have more attenuation, and the filter needs to be placed as close as possible to the connectors.

Besides the general PCB layout guidelines on TLC6C5748-Q1, it is also important to provide a low impedance return path for the signal traces. An integrated and continuous GND plane might not be easy for 2-layer PCB board, but it needs to be done as much as possible. For the signal traces, GSCLK, SIN, SCLK should be placed on the bottom layer only. It’s better not to use vias on these traces. While the signal traces are parallel, evenly spaced vias need to be put between them to have the GND plane integrated.

#FIG_Q5X_YW4_FWB shows the reference layout bottom layer (blue) and top layer (red).

GUID-37D64296-8ACA-4087-A4A6-7FA63D5BF876-low.jpg Figure 2-10 Bottom Layer of PCB Layout
GUID-29B40E72-8F16-49D8-ACC6-0FC729907C5C-low.jpg Figure 2-11 Top layer of PCB Layout