SLVAFU9 January   2025 TPS62840 , TPS62843

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Inverting Buck-Boost Topology
    1. 1.1 Concept
    2. 1.2 Output Current Calculations
    3. 1.3 VIN and VOUT Range
  5. 2Design Considerations
    1. 2.1 Additional Input Capacitor
    2. 2.2 Digital Input Pin Configurations
    3. 2.3 Startup Behavior and Switching Node Consideration
  6. 3External Component Selection
    1. 3.1 Inductor Selection
    2. 3.2 Capacitor Selection
  7. 4Typical Performance
  8. 5Summary
  9. 6References

2.2 Digital Input Pin Configurations

Because VOUT is the IC ground in this configuration, the EN pin must be referenced to VOUT instead of the ground. In a buck configuration, the specified threshold voltage for the enable pin in the product data sheet is 1.1V to be considered high and 0.4V to be considered low (see the TPS62840 product data sheet). In the inverting buck-boost configuration, however, the VOUT voltage is the reference; therefore, the high threshold is 1.1V + VOUT and the low threshold is 0.4V + VOUT. For example, if VOUT = -1.8V, the VEN is considered a high level for voltages above –0.7V and a low level for voltages below –1.4V. The same effect is true with the MODE and STOP pins. This behavior can cause difficulties enabling or disabling the part, since in some applications, the IC providing the EN signal cannot produce negative voltages. The level shifter shown in Figure 2-2 alleviates any problems associated with the offset EN threshold voltages by eliminating the need for negative EN signals.

EN Pin Level ShifterFigure 2-2 EN Pin Level Shifter

The positive signal that originally drove EN is instead tied to the gate of Q1 (SYS_EN). When Q1 is off (SYS_EN grounded), Q2 sees 0V across the VGS, and also remains off. In this state, the EN pin sees VOUT which is below the low level threshold and disables the device. When SYS_EN provides enough positive voltage to turn Q1 on (minimum VGS as specified in the MOSFET’s data sheet), the gate of Q2 is pulled low through Q1. This drives the VGS of Q2 negative and turns Q2 on. As a consequence, VIN ties to EN through Q2 and the pin is above the high level threshold, causing the device to turn on. Make sure that the VGD of Q2 remains within the MOSFET’s ratings during both enabled and disabled states. Failing to adhere to this constraint can result in damaged MOSFETs. The enable and disable sequence is illustrated in Figure 2-3 and Figure 2-4. The SYS_EN signal activates the enable circuit, and the G/D NODE signal represents the shared node between Q1 and Q2. The EN signal is the output of the circuit and goes from VIN to –VOUT properly enabling and disabling the device.

EN Pin Level Shifter on StartupFigure 2-3 EN Pin Level Shifter on Startup
EN Pin Level Shifter on ShutdownFigure 2-4 EN Pin Level Shifter on Shutdown