2 Understanding Full-scale and ADC Headroom

Years ago, high-speed data converters were designed on process nodes that supported voltage swings as large as 10 Vpp full-scale.

The converters were even single-ended. Setting the converter’s reference gave some flexibility to make the full-scale range unipolar or bipolar.

Today, the converter process nodes are small – 65nm or less – and the converter’s internal analog input front end is biased at <2 V AVDD. This makes for significantly lower headroom, which can become a challenge when signal chain designs need to interface with 1 or 2 Vpp full-scale ranges, where the RF stops and the ADC begins.

Today, most high-speed data converters employ differential inputs. This implies we only have one-fourth the signal swing to wrap around the common-mode voltage (VCM) bias, or each analog input handles one-half the swing. Figure 1 illustrates single-ended vs. differential signal properties and definitions.

The converter’s analog input VCM is important and needs to be satisfied by the external input network front end; otherwise, the converter can have other performance issues.

By dividing up the signal swing differentially, this interface enables you to maintain higher voltage levels across the full-scale range (that is, 1 or 2Vpp); therefore, the differential nature of the analog input enables a smaller process node.