SLVAFZ7A March   2025  – April 2025 ADC12DJ5200RF

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Understanding Full-scale and ADC Headroom
  6. 3Full-Scale Trade-offs
  7. 4Full-Scale Breakdown
  8. 5Summary
  9. 6References
  10. 7Revision History

Full-Scale Breakdown

Following is an example that illustrates the trade-offs involved when designing a high-speed matching network to the ADC. Baluns and frontend networks can add loss and additional noise figure to the overall signal chain, so it is pertinent to understand the input-drive trade-offs during the design and optimize the full-scale value. The input drive defines the amount of signal (in dBm) required to drive the converter at a full-scale range in front of the interface network – in this case, a passive balun network.

In the example, the ADC is the RF-sampling, 12-bit ADC12DJ5200RF from Texas Instruments and the balun is the BAL-0009SMG from Marki® Microwave. A front-end resistive network interfaces the balun differential outputs to the ADC differential inputs. See Figure 4-1.

 Example Front-End
                    Network Figure 4-1 Example Front-End Network

Next are the calculations. If no dBm calculator is handy, the recommendation is to download the latest TI 84 Plus app to your mobile phone.

The ADC12DJ5200RF has a default analog input full-scale range of 800-mVpp(Vfs) with a 100Ω (Radc) differential load internally which is calculated in terms of dBm:

Equation 1. P a d c   =   10 × log V f s 2 2 2 R a d c 0 . 001   o r   10 × log 800 m 2 2 2 100 0 . 001 = - 0 . 97   d B m

Since the input network is differential, the network can become a little difficult to crunch through the numbers. But by using the single-ended approach, the full-scale voltage at the input of the converter has a value of 400mVpp (Vfs/2) or -3.97dBm.

By using a front-end resistive network as described, calculate the voltage dividers to understand the losses required to achieve a 400 mVpp (Vfs/2) full-scale value.

Radc/2 = 50Ω and Rs form a resistive divider or

Equation 2. V a   =   V f s 2 × R a d c 2 + R s R a d c   =   0 . 47   V
which gives you a single-ended voltage input at Rs and Rt. Now, calculate the single-ended voltage at the balun output, or
Equation 3. V b   =   V a × R a d c 2 + R s | |   R t 2 + R s R a d c 2 + R s | | R t 2   =   0 . 57   V

You can make this single-ended voltage a differential voltage or 2×Vb or 1.13V = Vdiffbo. The power at the balun’s output is then

Equation 4. P b o   =   10 × log V d i f f b o 2 2 2 R a d c 0 . 001   =   + 2 . 06   d B m

Now for the fun part: either consult the data sheet of the prospective balun or measure the balun on your nearest four-port vector network analyzer and take an SDS21 measurement. This can yield a single-ended-to-differential measurement and provide the correct insertion loss across the balun. In this example, measuring the BAL-0009SMG yields a loss of 4.2dB at 1GHz. See Figure 4-2.

 SDS21 Insertion lLoss Plot of
                    the Marki Microwave BAL-0009SMG Balun Figure 4-2 SDS21 Insertion lLoss Plot of the Marki Microwave BAL-0009SMG Balun

Adding the balun losses to the output power found at the balun’s output (resistive network loss) determines what the input drive is: 2.06 + 4.2 or +6.26dBm. +6.26dBm is the required input amplitude required to drive the analog input signal on the primary of the balun to the full-scale range of the ADC.

Therefore, the total losses from top to bottom are 6.26 + 0.97, or a 7.26dBm loss. Remember the Padc equation (with the result of -0.97dBm) to achieve the full-scale value? Add that result back in, also to achieve 0dB fullscale of the ADC.

A quick note on noise figure: When designing an analog receiver chain, the loss in the balun and frontend network counts as well. For this case, the noise figure addition can be the loss found or 6.26dBm, which is a value of 1.3Vpp vs. the default full-scale value of 800mVpp. This means 20×log(1.3/0.8) = 4.22dB of additional noise figure in the receiver signal chain.

Looking at a different approach: measuring in the lab with the ADC12DJ5200RF evaluation module. Using the signal generator, dial in the output level until the converter is very near the full-scale value at 1GHz. In this case, the input full-scale value was +6.3 dBm from the signal generator reading. Keep in mind that balun variance and cable/connector losses can cause some differences. See Figure 4-3.

 HSDC-Pro FFT Plot Showing an
                    Unfiltered Intermediate Frequency of 1GHz at -0.01dBFS Figure 4-3 HSDC-Pro FFT Plot Showing an Unfiltered Intermediate Frequency of 1GHz at -0.01dBFS