SLVAG34 August   2026 TPS650362-Q1 , TPS65219-Q1 , TPS65224-Q1

 

  1.   1
  2.   Abstract
  3. 1Introduction
  4. 2Causes of PMICs Failing to Resume Operation Due to Slow Voltage Ramp Tests
    1. 2.1 Two Input Undervoltage Lockout (UVLO) Mechanisms of PMICs
    2. 2.2 Repeated PVIN_B1_UVLO Triggers Force the PMIC into WT_PWR_REC State
    3. 2.3 Reasons Why Slow Voltage Ramp Causes the PMIC to Enter WT_PWR_REC State
  5. 3Common Solutions for Wide-Input PMICs
    1. 3.1 Increase the Gap Between PVIN_B1_UVLO Rising and Falling
    2. 3.2 Replace Reverse-Polarity Protection Diode with an Ideal Diode
    3. 3.3 TPS650362-Q1 Can Use Resistive Discharge Instead of Active Discharge
  6. 4Common Solutions for Low-Input PMICs
    1. 4.1 Adjusting Primary BUCK Loop Stability
    2. 4.2 Prevent Primary BUCK from Entering Dropout Mode During Slow Ramp Testing
  7. 5Non-Functional Safety Systems Can Disable/Mask RECOV_CNT_THR to Avoid Entering SAFE/OFF States
  8. 6References

2.3 Reasons Why Slow Voltage Ramp Causes the PMIC to Enter WT_PWR_REC State

PVIN_B1_UVLO is a common undervoltage protection mechanism; however, in slow voltage ramp tests, input voltage stays near the PVIN_B1_UVLO threshold for long periods, easily causing repeated UVLO triggers that push the PMIC into WT_PWR_REC state. The reason is that each trigger of PVIN_B1_UVLO Rising/Falling turns PMIC outputs ON/OFF, causing load current changes on the input power supply, effectively dumping or applying load and inducing severe voltage overshoots/undershoots.

During slow voltage ramp testing, the input voltage lingers between PVIN_B1_UVLO Rising and Falling thresholds; excessive overshoot/undershoot triggers PVIN_B1 UVLO Falling/Rising, causing repeated transitions in/out of SAFE state. When the RECOVERY count reaches RECOV_CNT_THR, the PMIC enters WT_PWR_REC state, leaving the PMIC unable to operate even after power recovers, requiring a VSYS power cycle to clear the RECOVERY count and restart the PMIC.

Figure 2-3 Taking TPS650362-Q1 as an example in a slow decrease test with PVIN_B1_UVLO Falling = 4.5V, PVIN_B1_UVLO Rising = 5.2V, and RECOV_CNT_THR = 15. PVIN_B1_VIN repeatedly triggers PVIN_B1_UVLO due to overshoot/undershoot; after exceeding 15 times, the PMIC yields no output even when PVIN_B1 voltage exceeds PVIN_B1_UVLO Rising =5.2V.

TPS650362-Q1 yields no output after repeated PVIN_B1_UVLO triggers during slow decrease testFigure 2-3 TPS650362-Q1 yields no output after repeated PVIN_B1_UVLO triggers during slow decrease test