SLVAG34 August 2026 TPS650362-Q1 , TPS65219-Q1 , TPS65224-Q1
PVIN_B1_UVLO features programmable Falling and Rising thresholds; as input voltage rises, it must reach PVIN_B1_UVLO Rising to enable output, and as input voltage drops, reaching PVIN_B1_UVLO Falling turns output off.
When the input voltage of TPS650362-Q1 drops below PVIN_B1_UVLO Falling, outputs turn off, the PMIC enters SAFE state, and an error interrupt is generated. In the SAFE state, if input voltage exceeds PVIN_B1 UVLO Rising and no other error interrupts exist, the PMIC re-enters Active state. Each time the PMIC enters SAFE state and recovers, the RECOV_CNT counter increments by +1. When the count reaches RECOV_CNT_THR, the PMIC enters WT_PWR_REC state, requiring a power cycle on VSYS to restart the PMIC. The RECOV_CNT_THR threshold defaults to 15 times; the RECOV_CNT counter can be cleared by register operation or power-cycling to trigger VSYS_UVLO restart.
The input protection mechanism of TPS65224-Q1 is similar to that of TPS650362-Q1, where triggering VCCA0V_TH leads to a PMIC Warm Reset and transitions to To SAFE state. When input voltage exceeds VCCA0V_TH, the PMIC re-enters Active state. Each transition to To SAFE increments RECOV_CNT by +1; once the count exceeds RECOV_CNT_THR, TPS65224-Q1 remains in SAFE_RECOVER state, requiring a power-cycle to restart the PMIC.
Figure 2-2 TPS650362-Q1 state machine