SLVSBF0D July   2012  – July 2026 TPS53015

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Drivers
      2. 6.3.2 5-Volt Regulator
      3. 6.3.3 Soft Start and Prebiased Soft-Start Time
      4. 6.3.4 Overcurrent Protection
      5. 6.3.5 Overvoltage and Undervoltage Protection
      6. 6.3.6 UVLO Protection
      7. 6.3.7 Thermal Shutdown
      8. 6.3.8 Power Good
    4. 6.4 Device Functional Modes
      1. 6.4.1 PWM Operation
      2. 6.4.2 Auto-skip Eco-Mode Control
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Determine the Inductance Value
        2. 7.2.2.2 Output Capacitor
        3. 7.2.2.3 Input Capacitor
        4. 7.2.2.4 Bootstrap Capacitor
        5. 7.2.2.5 VREG5 Capacitor
        6. 7.2.2.6 Choose Output Voltage Resistors
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

6.4.1 PWM Operation

The main control loop of the TPS53015 device is an adaptive on-time pulse width modulation (PWM) controller that supports a proprietary D-CAP2 control topology . D-CAP2 control topology combines constant on-time control with an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with both low ESR and ceramic output capacitors. D-CAP2 control topology is stable even with virtually no ripple at the output. At the beginning of each cycle, the high-side MOSFET is turned on. this MOSFET is turned off when the internal timer expires. This timer is set by the converter input voltage VIN, and the output voltage (VOUT) to maintain a pseudo-fixed frequency over the input voltage range, therefore called adaptive on-time control. The timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the nominal output voltage. An internal ramp is added to the reference voltage to simulate output ripple, eliminating the need for ESR induced output ripple from D-CAP2 control topology.