SLVSDR2C November   2018  – March 2025 ADC12DJ3200QML-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics: DC Specifications
    6. 5.6  Electrical Characteristics: Power Consumption
    7. 5.7  Electrical Characteristics: AC Specifications (Dual-Channel Mode)
    8. 5.8  Electrical Characteristics: AC Specifications (Single-Channel Mode)
    9. 5.9  Timing Requirements
    10. 5.10 Switching Characteristics
    11. 5.11 Timing Diagrams
    12. 5.12 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Analog Inputs
        1. 6.3.1.1 Analog Input Protection
        2. 6.3.1.2 Full-Scale Voltage (VFS) Adjustment
        3. 6.3.1.3 Analog Input Offset Adjust
      2. 6.3.2 ADC Core
        1. 6.3.2.1 ADC Theory of Operation
        2. 6.3.2.2 ADC Core Calibration
        3. 6.3.2.3 ADC Overrange Detection
        4. 6.3.2.4 Code Error Rate (CER)
      3. 6.3.3 Timestamp
      4. 6.3.4 Clocking
        1. 6.3.4.1 Noiseless Aperture Delay Adjustment (tAD Adjust)
        2. 6.3.4.2 Aperture Delay Ramp Control (TAD_RAMP)
        3. 6.3.4.3 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
          1. 6.3.4.3.1 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
          2. 6.3.4.3.2 Automatic SYSREF Calibration
      5. 6.3.5 Digital Down Converters (Dual-Channel Mode Only)
        1. 6.3.5.1 Numerically-Controlled Oscillator and Complex Mixer
          1. 6.3.5.1.1 NCO Fast Frequency Hopping (FFH)
          2. 6.3.5.1.2 NCO Selection
          3. 6.3.5.1.3 Basic NCO Frequency Setting Mode
          4. 6.3.5.1.4 Rational NCO Frequency Setting Mode
          5. 6.3.5.1.5 NCO Phase Offset Setting
          6. 6.3.5.1.6 NCO Phase Synchronization
        2. 6.3.5.2 Decimation Filters
        3. 6.3.5.3 Output Data Format
        4. 6.3.5.4 Decimation Settings
          1. 6.3.5.4.1 Decimation Factor
          2. 6.3.5.4.2 DDC Gain Boost
      6. 6.3.6 JESD204B Interface
        1. 6.3.6.1 Transport Layer
        2. 6.3.6.2 Scrambler
        3. 6.3.6.3 Link Layer
          1. 6.3.6.3.1 Code Group Synchronization (CGS)
          2. 6.3.6.3.2 Initial Lane Alignment Sequence (ILAS)
          3. 6.3.6.3.3 8b, 10b Encoding
          4. 6.3.6.3.4 Frame and Multiframe Monitoring
        4. 6.3.6.4 Physical Layer
          1. 6.3.6.4.1 SerDes Pre-Emphasis
        5. 6.3.6.5 JESD204B Enable
        6. 6.3.6.6 Multi-Device Synchronization and Deterministic Latency
        7. 6.3.6.7 Operation in Subclass 0 Systems
      7. 6.3.7 Alarm Monitoring
        1. 6.3.7.1 NCO Upset Detection
        2. 6.3.7.2 Clock Upset Detection
      8. 6.3.8 Temperature Monitoring Diode
      9. 6.3.9 Analog Reference Voltage
    4. 6.4 Device Functional Modes
      1. 6.4.1 Dual-Channel Mode
      2. 6.4.2 Single-Channel Mode (DES Mode)
      3. 6.4.3 JESD204B Modes
        1. 6.4.3.1 JESD204B Output Data Formats
        2. 6.4.3.2 Dual DDC and Redundant Data Mode
      4. 6.4.4 Power-Down Modes
      5. 6.4.5 Test Modes
        1. 6.4.5.1 Serializer Test-Mode Details
        2. 6.4.5.2 PRBS Test Modes
        3. 6.4.5.3 Ramp Test Mode
        4. 6.4.5.4 Short and Long Transport Test Mode
          1. 6.4.5.4.1 Short Transport Test Pattern
          2. 6.4.5.4.2 Long Transport Test Pattern
        5. 6.4.5.5 D21.5 Test Mode
        6. 6.4.5.6 K28.5 Test Mode
        7. 6.4.5.7 Repeated ILA Test Mode
        8. 6.4.5.8 Modified RPAT Test Mode
      6. 6.4.6 Calibration Modes and Trimming
        1. 6.4.6.1 Foreground Calibration Mode
        2. 6.4.6.2 Background Calibration Mode
        3. 6.4.6.3 Low-Power Background Calibration (LPBG) Mode
      7. 6.4.7 Offset Calibration
      8. 6.4.8 Trimming
      9. 6.4.9 Offset Filtering
    5. 6.5 Programming
      1. 6.5.1 Using the Serial Interface
        1. 6.5.1.1 SCS
        2. 6.5.1.2 SCLK
        3. 6.5.1.3 SDI
        4. 6.5.1.4 SDO
        5. 6.5.1.5 Streaming Mode
    6. 6.6 Register Maps
      1. 6.6.1 Register Descriptions
      2. 6.6.2 SYSREF Calibration Registers (0x2B0 to 0x2BF)
      3. 6.6.3 Alarm Registers (0x2C0 to 0x2C2)
  8. 7 Application Information Disclaimer
    1. 7.1 Application Information
      1. 7.1.1 Analog Inputs
      2. 7.1.2 Analog Input Bandwidth
      3. 7.1.3 Clocking
      4. 7.1.4 Radiation Environment Recommendations
        1. 7.1.4.1 Single Event Latch-Up (SEL)
        2. 7.1.4.2 Single Event Functional Interrupt (SEFI)
        3. 7.1.4.3 Single Event Upset (SEU)
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 RF Input Signal Path
        2. 7.2.2.2 Calculating Values of AC-Coupling Capacitors
      3. 7.2.3 Application Curves
    3. 7.3 Initialization Set Up
    4.     Power Supply Recommendations
      1. 7.4.1 Power Sequencing
    5. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Third-Party Products Disclaimer
    4. 8.4 Receiving Notification of Documentation Updates
    5. 8.5 Support Resources
    6. 8.6 Trademarks
    7. 8.7 Electrostatic Discharge Caution
    8. 8.8 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.12 Typical Characteristics

Typical values are at TA = 25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000), input signal applied to INA± in single-channel modes, fIN = 347MHz, AIN = –1dBFS, fCLK = maximum-rated clock frequency, filtered 1-VPP sine-wave clock, JMODE = 1, and background calibration (unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD and ENOB exclude DC and fS / 2 fixed spurs; SFDR results exclude DC and signal-independent interleaving spurs (fS / 4 and fS / 2 spurs)

ADC12DJ3200QML-SP SNR vs Input Frequency
JMODE 3, fS = 3200MHz, foreground (FG) and background (BG) calibration
Figure 5-4 SNR vs Input Frequency
ADC12DJ3200QML-SP SINAD vs Input Frequency
JMODE 3, fS = 3200MHz, FG and BG calibration
Figure 5-6 SINAD vs Input Frequency
ADC12DJ3200QML-SP ENOB vs Input Frequency
JMODE 3, fS = 3200MHz, FG and BG calibration
Figure 5-8 ENOB vs Input Frequency
ADC12DJ3200QML-SP SFDR vs Input Frequency
JMODE 3, fS = 3200MHz, FG and BG calibration
Figure 5-10 SFDR vs Input Frequency
ADC12DJ3200QML-SP HD2 and HD3 vs Input Frequency
JMODE 3, fS = 3200MHz, FG calibration
Figure 5-12 HD2 and HD3 vs Input Frequency
ADC12DJ3200QML-SP Worst Interleaving Spur vs Input Frequency
JMODE 3, fS = 3200MHz, FG calibration, includes fS / 2 – fIN spur only
Figure 5-14 Worst Interleaving Spur vs Input Frequency
ADC12DJ3200QML-SP SNR vs Sampling Rate
JMODE 3, FG and BG calibration, fIN = 2482MHz, AIN = –1dBFS
Figure 5-16 SNR vs Sampling Rate
ADC12DJ3200QML-SP SINAD vs Sampling Rate
JMODE 3, FG and BG calibration, fIN = 2482MHz, AIN = –1dBFS
Figure 5-18 SINAD vs Sampling Rate
ADC12DJ3200QML-SP ENOB vs Sampling Rate
JMODE 3, FG and BG calibration, fIN = 2482MHz, AIN = –1dBFS
Figure 5-20 ENOB vs Sampling Rate
ADC12DJ3200QML-SP SFDR vs Sampling Rate
JMODE 3, FG and BG calibration, fIN = 2482MHz, AIN = –1dBFS
Figure 5-22 SFDR vs Sampling Rate
ADC12DJ3200QML-SP SNR vs Input Power
JMODE 3, FG calibration, fS = 3200MSPS
Figure 5-24 SNR vs Input Power
ADC12DJ3200QML-SP SFDR vs Input Power
JMODE 3, FG calibration, fS = 3200MSPS
Figure 5-26 SFDR vs Input Power
ADC12DJ3200QML-SP SNR vs Clock Amplitude
JMODE 1, FG calibration, fS = 6400MSPS, AIN = –1dBFS
Figure 5-28 SNR vs Clock Amplitude
ADC12DJ3200QML-SP Single-Tone FFT at fIN = 347MHz, AIN = –1dBFS
JMODE 3, FG calibration, fS = 3200MSPS, SNR = 56.3dBFS, SFDR = 69dBFS, ENOB = 9.0 bits
Figure 5-30 Single-Tone FFT at fIN = 347MHz, AIN = –1dBFS
ADC12DJ3200QML-SP Single-Tone FFT at fIN = 2482MHz, AIN = –1dBFS
JMODE 3, FG calibration, fS = 3200MSPS, SNR = 55.3dBFS, SFDR = 66dBFS, ENOB = 8.8 bits
Figure 5-32 Single-Tone FFT at fIN = 2482MHz, AIN = –1dBFS
ADC12DJ3200QML-SP Single-Tone FFT at fIN = 2482MHz, AIN = –7dBFS
JMODE 3, FG calibration, fS = 3200MSPS, SNR = 56.2dBFS, SFDR = 77dBFS, ENOB = 9.0 bits
Figure 5-34 Single-Tone FFT at fIN = 2482MHz, AIN = –7dBFS
ADC12DJ3200QML-SP Single-Tone FFT at fIN = 4997MHz, AIN = –1dBFS
JMODE 3, FG calibration, fS = 3200MSPS, SNR = 53dBFS, SFDR = 59dBFS, ENOB = 8.2 bits
Figure 5-36 Single-Tone FFT at fIN = 4997MHz, AIN = –1dBFS
ADC12DJ3200QML-SP Single-Tone FFT at fIN = 8197MHz, AIN = –1dBFS
JMODE 3, FG calibration, fS = 3200MSPS, SNR = 51.1dBFS, SFDR = 53dBFS, ENOB = 7.8 bits
Figure 5-38 Single-Tone FFT at fIN = 8197MHz, AIN = –1dBFS
ADC12DJ3200QML-SP Two-Tone FFT at fIN = 347MHz, AIN = –1dBFS
JMODE 3, FG calibration, fS = 3200MSPS, f1 = 342MHz, f2 = 352MHz, AIN = –7dBFS per tone, SFDR = –73dBFS, IMD3 = –87dBFS, IMD2 = –74dBFS
Figure 5-40 Two-Tone FFT at fIN = 347MHz, AIN = –1dBFS
ADC12DJ3200QML-SP Two-Tone FFT at fIN = 2482MHz, AIN = –1dBFS
JMODE 3, FG calibration, fS = 3200MSPS, f1 = 2477MHz, f2 = 2487MHz, AIN = –7dBFS per tone, SFDR = –70dBFS, IMD3 = –74dBFS, IMD2 = –70dBFS
Figure 5-42 Two-Tone FFT at fIN = 2482MHz, AIN = –1dBFS
ADC12DJ3200QML-SP Two-Tone FFT at fIN = 4997MHz, AIN = –1dBFS
JMODE 3, FG calibration, fS = 3200MSPS, f1 = 4992MHz, f2 = 5002MHz, AIN = –7dBFS per tone, SFDR = –62dBFS, IMD3 = –63dBFS, IMD2 = –80dBFS
Figure 5-44 Two-Tone FFT at fIN = 4997MHz, AIN = –1dBFS
ADC12DJ3200QML-SP DNL vs Code
JMODE 1, FG calibration, fS = 6400MSPS, fIN = 99.97MHz
Figure 5-46 DNL vs Code
ADC12DJ3200QML-SP Performance vs Temperature
JMODE 1, BG calibration, fS = 6400MSPS, fIN = 2482MHz, AIN = –1dBFS
Figure 5-48 Performance vs Temperature
ADC12DJ3200QML-SP SNR vs Temperature and Calibration Mode
JMODE 3, fS = 3200MSPS, fIN = 347MHz, AIN = –1dBFS
Figure 5-50 SNR vs Temperature and Calibration Mode
ADC12DJ3200QML-SP SINAD vs Temperature and Calibration Mode
JMODE 3, fS = 3200MSPS, fIN = 347MHz, AIN = –1dBFS
Figure 5-52 SINAD vs Temperature and Calibration Mode
ADC12DJ3200QML-SP ENOB vs Temperature and Calibration Mode
JMODE 3, fS = 3200MSPS, fIN = 347MHz, AIN = –1dBFS
Figure 5-54 ENOB vs Temperature and Calibration Mode
ADC12DJ3200QML-SP SFDR vs Temperature and Calibration Mode
JMODE 3, fS = 3200MSPS, fIN = 347MHz, AIN = –1dBFS
Figure 5-56 SFDR vs Temperature and Calibration Mode
ADC12DJ3200QML-SP Performance vs Supply Voltage
JMODE 1, FG calibration, fS = 6400MSPS, fIN = 2482MHz, AIN = –1dBFS
Figure 5-58 Performance vs Supply Voltage
ADC12DJ3200QML-SP VA19 Supply Current vs Clock Rate
JMODE 1, fIN = 2482MHz, AIN = –1dBFS
Figure 5-60 VA19 Supply Current vs Clock Rate
ADC12DJ3200QML-SP VD11 Supply Current vs Clock Rate
JMODE 1, fIN = 2482MHz, AIN = –1dBFS
Figure 5-62 VD11 Supply Current vs Clock Rate
ADC12DJ3200QML-SP Supply Current vs JMODE
fCLK = 3200MHz, FG calibration, fIN = 2482MHz, AIN = –1dBFS
Figure 5-64 Supply Current vs JMODE
ADC12DJ3200QML-SP Power Consumption vs JMODE
fCLK = 3200MHz, fIN = 2482MHz, AIN = –1dBFS
Figure 5-66 Power Consumption vs JMODE
ADC12DJ3200QML-SP Gain Response vs Input Frequency
Figure 5-68 Gain Response vs Input Frequency
ADC12DJ3200QML-SP Background Calibration Core Transition (AC Signal Zoomed)
JMODE 1, fS = 6400MSPS, fIN = 3199.9MHz
Figure 5-70 Background Calibration Core Transition (AC Signal Zoomed)
ADC12DJ3200QML-SP Background Calibration Core Transition (DC Signal Zoomed)
JMODE 1, fS = 6400MSPS, DC input
Figure 5-72 Background Calibration Core Transition (DC Signal Zoomed)
ADC12DJ3200QML-SP SNR vs Input Frequency
JMODE 1, fS = 6400MHz, FG and BG calibration
Figure 5-5 SNR vs Input Frequency
ADC12DJ3200QML-SP SINAD vs Input Frequency
JMODE 1, fS = 6400MHz, FG and BG calibration
Figure 5-7 SINAD vs Input Frequency
ADC12DJ3200QML-SP ENOB vs Input Frequency
JMODE 1, fS = 6400MHz, FG and BG calibration
Figure 5-9 ENOB vs Input Frequency
ADC12DJ3200QML-SP SFDR vs Input Frequency
JMODE 1, fS = 6400MHz, FG and BG calibration
Figure 5-11 SFDR vs Input Frequency
ADC12DJ3200QML-SP HD2 and HD3 vs Input Frequency
JMODE 1, fS = 6400MHz, FG calibration
Figure 5-13 HD2 and HD3 vs Input Frequency
ADC12DJ3200QML-SP Worst Interleaving Spur vs Input Frequency
JMODE 1, fS = 6400MHz, FG calibration, includes fS / 2 – fIN and fS /4 ± fIN spurs only
Figure 5-15 Worst Interleaving Spur vs Input Frequency
ADC12DJ3200QML-SP SNR vs Sampling Rate
JMODE 1, FG and BG calibration, fIN = 2482MHz, AIN = –1dBFS
Figure 5-17 SNR vs Sampling Rate
ADC12DJ3200QML-SP SINAD vs Sampling Rate
JMODE 1, FG and BG calibration, fIN = 2482MHz, AIN = –1dBFS
Figure 5-19 SINAD vs Sampling Rate
ADC12DJ3200QML-SP ENOB vs Sampling Rate
JMODE 1, FG and BG calibration, fIN = 2482MHz, AIN = –1dBFS
Figure 5-21 ENOB vs Sampling Rate
ADC12DJ3200QML-SP SFDR vs Sampling Rate
JMODE 1, FG and BG calibration, fIN = 2482MHz, AIN = –1dBFS
Figure 5-23 SFDR vs Sampling Rate
ADC12DJ3200QML-SP SNR vs Input Power
JMODE 1, FG calibration, fS = 6400MSPS
Figure 5-25 SNR vs Input Power
ADC12DJ3200QML-SP SFDR vs Input Power
JMODE 1, FG calibration, fS = 6400MSPS
Figure 5-27 SFDR vs Input Power
ADC12DJ3200QML-SP SFDR vs Clock Amplitude
JMODE 1, FG calibration, fS = 6400MSPS, AIN = –1dBFS
Figure 5-29 SFDR vs Clock Amplitude
ADC12DJ3200QML-SP Single-Tone FFT at fIN = 347MHz, AIN = –1dBFS
JMODE 1, FG calibration, fS = 6400MSPS, SNR = 55.9dBFS, SFDR = 68dBFS, ENOB = 8.9 bits
Figure 5-31 Single-Tone FFT at fIN = 347MHz, AIN = –1dBFS
ADC12DJ3200QML-SP Single-Tone FFT at fIN = 2482MHz, AIN = –1dBFS
JMODE 1, FG calibration, fS = 6400MSPS, SNR = 55.5dBFS, SFDR = 52dBFS, ENOB = 8.1 bits
Figure 5-33 Single-Tone FFT at fIN = 2482MHz, AIN = –1dBFS
ADC12DJ3200QML-SP Single-Tone FFT at fIN = 2482MHz, AIN = –7dBFS
JMODE 1, FG calibration, fS = 6400MSPS, SNR = 56.1dBFS, SFDR = 58dBFS, ENOB = 8.6 bits
Figure 5-35 Single-Tone FFT at fIN = 2482MHz, AIN = –7dBFS
ADC12DJ3200QML-SP Single-Tone FFT at fIN = 4997MHz, AIN = –1dBFS
JMODE 1, FG calibration, fS = 6400MSPS, SNR = 53.5dBFS, SFDR = 61dBFS, ENOB = 8.2 bits
Figure 5-37 Single-Tone FFT at fIN = 4997MHz, AIN = –1dBFS
ADC12DJ3200QML-SP Single-Tone FFT at fIN = 8197MHz, AIN = –1dBFS
JMODE 1, FG calibration, fS = 6400MSPS, SNR = 51.4dBFS, SFDR = 48dBFS, ENOB = 7.3 bits
Figure 5-39 Single-Tone FFT at fIN = 8197MHz, AIN = –1dBFS
ADC12DJ3200QML-SP Two-Tone FFT at fIN = 347MHz, AIN = –1dBFS
JMODE 1, FG calibration, fS = 6400MSPS, f1 = 342MHz, f2 = 352MHz, AIN = –7dBFS per tone, SFDR = –70dBFS, IMD3 = –91dBFS, IMD2 = –71dBFS
Figure 5-41 Two-Tone FFT at fIN = 347MHz, AIN = –1dBFS
ADC12DJ3200QML-SP Two-Tone FFT at fIN = 2482MHz, AIN = –1dBFS
JMODE 1, FG calibration, fS = 6400MSPS, f1 = 2477MHz, f2 = 2487MHz, AIN = –7dBFS per tone, SFDR = –58dBFS, IMD3 = –70dBFS, IMD2 = –75dBFS
Figure 5-43 Two-Tone FFT at fIN = 2482MHz, AIN = –1dBFS
ADC12DJ3200QML-SP Two-Tone FFT at fIN = 4997MHz, AIN = –1dBFS
JMODE 1, FG calibration, fS = 6400MSPS, f1 = 4992MHz, f2 = 5002MHz, AIN = –7dBFS per tone, SFDR = –62dBFS, IMD3 = –65dBFS, IMD2 = –71dBFS
Figure 5-45 Two-Tone FFT at fIN = 4997MHz, AIN = –1dBFS
ADC12DJ3200QML-SP INL vs Code
JMODE 1, FG calibration, fS = 6400MSPS, fIN = 99.97MHz
Figure 5-47 INL vs Code
ADC12DJ3200QML-SP Performance vs Temperature
JMODE 1, FG calibration, fS = 6400MSPS, fIN = 2482MHz, AIN = –1dBFS
Figure 5-49 Performance vs Temperature
ADC12DJ3200QML-SP SNR vs Temperature and Calibration Mode
JMODE 1, fS = 6400MSPS, fIN = 347MHz, AIN = –1dBFS
Figure 5-51 SNR vs Temperature and Calibration Mode
ADC12DJ3200QML-SP SINAD vs Temperature and Calibration Mode
JMODE 1, fS = 6400MSPS, fIN = 347MHz, AIN = –1dBFS
Figure 5-53 SINAD vs Temperature and Calibration Mode
ADC12DJ3200QML-SP ENOB vs Temperature and Calibration Mode
JMODE 1, fS = 6400MSPS, fIN = 347MHz, AIN = –1dBFS
Figure 5-55 ENOB vs Temperature and Calibration Mode
ADC12DJ3200QML-SP SFDR vs Temperature and Calibration Mode
JMODE 1, fS = 6400MSPS, fIN = 347MHz, AIN = –1dBFS
Figure 5-57 SFDR vs Temperature and Calibration Mode
ADC12DJ3200QML-SP Performance vs Supply Voltage
JMODE 1, FG calibration, fS = 6400MSPS, fIN = 2482MHz, AIN = –1dBFS
Figure 5-59 Performance vs Supply Voltage
ADC12DJ3200QML-SP VA11 Supply Current vs Clock Rate
JMODE 1, fIN = 2482MHz, AIN = –1dBFS
Figure 5-61 VA11 Supply Current vs Clock Rate
ADC12DJ3200QML-SP Power Consumption vs Clock Rate
JMODE 1, fIN = 2482MHz, AIN = –1dBFS
Figure 5-63 Power Consumption vs Clock Rate
ADC12DJ3200QML-SP Supply Current vs JMODE
fCLK = 3200MHz, BG calibration, fIN = 2482MHz, AIN = –1dBFS
Figure 5-65 Supply Current vs JMODE
ADC12DJ3200QML-SP Power Consumption vs Temperature
JMODE 1, fS = 6400MSPS, fIN = 2482MHz, AIN = –1dBFS
Figure 5-67 Power Consumption vs Temperature
ADC12DJ3200QML-SP Background Calibration Core Transition (AC Signal)
JMODE 1, fS = 6400MSPS, fIN = 3199.9MHz
Figure 5-69 Background Calibration Core Transition (AC Signal)
ADC12DJ3200QML-SP Background Calibration Core Transition (DC Signal)
JMODE 1, fS = 6400MSPS, DC input
Figure 5-71 Background Calibration Core Transition (DC Signal)