12-bit, dual 3.2-GSPS or single 6.4-GSPS, RF-sampling analog-to-digital converter (ADC) - aerospace
Product details
Parameters
Package | Pins | Size
Features
- ADC core:
- 12-Bit resolution
- Up to 6.4 GSPS in single-channel mode
- Up to 3.2 GSPS in dual-channel mode
- Noise floor (no signal, VFS = 1.0 VPP-DIFF):
- Dual-channel mode: –149.5 dBFS/Hz
- Single-channel mode: –152.4 dBFS/Hz
- Peak noise power ratio (NPR): 45.4 dB
- Buffered analog inputs with VCMI of 0 V:
- Analog input bandwidth (–3 dB): 7 GHz
- Usable input frequency range: >10 GHz
- Full-scale input voltage (VFS, default): 0.8 VPP
- Noiseless aperture delay (tAD) adjustment:
- Precise sampling control: 19-fs step size
- Temperature and voltage invariant delays
- Easy-to-use synchronization features
- Automatic SYSREF timing calibration
- Timestamp for sample marking
- JESD204B subclass-1 compliant interface:
- Maximum lane rate: 12.8 Gbps
- Up to 16 lanes allows reduced lane rate
- Digital down-converters in dual-channel mode:
- Real output: DDC bypass or 2x decimation
- Complex output: 4x, 8x, or 16x decimation
- Radiation performance:
- Total Ionizing Dose (TID): 300 krad (Si)
- Single Event Latchup (SEL): 120 MeV-cm2/mg
- Single Event Upset (SEU) immune registers
- Power consumption: 3.0 W
All trademarks are the property of their respective owners.
Description
The ADC12DJ3200QML-SP device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from dc to above 10 GHz. In dual-channel mode, the ADC12DJ3200QML-SP can sample up to 3200 MSPS. In single-channel mode, the device can sample up to 6400 MSPS. Programmable tradeoffs in channel count (dual-channel mode) and Nyquist bandwidth (single-channel mode) allow development of flexible hardware that meets the needs of both high channel count or wide instantaneous signal bandwidth applications. Full-power input bandwidth (–3 dB) of 7.0 GHz, with usable frequencies exceeding the –3-dB point in both dual- and single-channel modes, allows direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.
The ADC12DJ3200QML-SP uses a high-speed JESD204B output interface with up to 16 serialized lanes and subclass-1 compliance for deterministic latency and multidevice synchronization. The serial output lanes support up to 12.8 Gbps, and can be configured to trade off bit rate and number of lanes. Innovative synchronization features, including noiseless aperture delay (tAD) adjustment and SYSREF windowing, simplify system design for synthetic aperture radar (SAR) and phased-array MIMO communications. Optional digital down converters (DDCs) in dual-channel mode allow for reduction in interface rate (real and complex decimation modes) and digital mixing of the signal (complex decimation modes only).
Technical documentation
Design & development
For additional terms or required resources, click any title below to view the detail page where available.Hardware development
Description
The ADC12DJ3200 evaluation module (EVM) allows for the evaluation of device ADC12DJ3200. The ADC12DJ3200 is a low-power, 12-bit, dual 3.2-GSPS/single 6.4-GSPS, RF-sampling analog-to-digital converter (ADC) with a buffered analog input, integrated digital down converter with programmable NCO and (...)
Features
- Flexible transformer-coupled analog input to allow for a variety of sources and frequencies
- Easy-to-use software GUI to configure ADC12DJ3200, LMX2582, and LMK04828 devices for a variety of configurations through a USB interface
- Quickly evaluate ADC performance through High-Speed Data Converter Pro (...)
Description
The ADC12DJ3200EVMCVAL is an evaluation module (EVM) that evaluates the ADC12DJ3200QML-SP device. ADC12DJ3200QML-SP is a space-grade, low-power, 12-bit, dual 3.2-GSPS/single 6.4-GSPS, RF-sampling analog-to-digital converter (ADC) with a buffered analog input, integrated digital down converter (...)
Features
- Flexible transformer-coupled analog input to allow for a variety of sources and frequencies
- Easy-to-use software GUI to configure ADC12DJ3200QML-SP, LMX2582, and LMK04832 devices for a variety of configurations through a USB interface
- Quickly evaluate ADC performance through high-speed data converter (...)
Software development
Features
- Compatible with JEDEC JESD204a/b/c protocols
- Supports subclass 1 deterministic latency and multidevice synchronization
- Supported lane rates
- Up to 16.375 Gbps in 8b/10b mode
- Up to 20 Gbps in 64b/66b mode
- Supports all protocol related error detection and reporting features
- Integrated transport layer (...)
Design tools & simulation
Features
- Leverages Cadence PSpice Technology
- Preinstalled library with a suite of digital models to enable worst-case timing analysis
- Dynamic updates ensure you have access to most current device models
- Optimized for simulation speed without loss of accuracy
- Supports simultaneous analysis of multiple products
- (...)
CAD/CAE symbols
| Package | Pins | Download |
|---|---|---|
| CCGA (NWE) | 196 | View options |
| CLGA (ZMX) | 196 | View options |
Ordering & quality
- RoHS
- REACH
- Device marking
- Lead finish/Ball material
- MSL rating/Peak reflow
- MTBF/FIT estimates
- Material content
- Qualification summary
- Ongoing reliability monitoring
Support & training
TI E2E™ forums with technical support from TI engineers
Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.
If you have questions about quality, packaging or ordering TI products, see TI support.