Home Data converters Analog-to-digital converters (ADCs) High-speed ADCs (>10MSPS)
Home
Data converters
Analog-to-digital converters (ADCs)
High-speed ADCs (>10MSPS)

ADC12DJ3200QML-SP

ACTIVE

12-bit, dual 3.2-GSPS or single 6.4-GSPS, RF-sampling analog-to-digital converter (ADC) - aerospace

Order now
Data sheet

ADC12DJ3200QML-SP

ACTIVE
Data sheet Order now

Product details

Sample rate (Max) (MSPS) 3200, 6400 Resolution (Bits) 12 Number of input channels 2, 1 Interface type JESD204B Analog input BW (MHz) 7300 Features Ultra High Speed Rating Space Input range (Vp-p) 0.8 Power consumption (Typ) (mW) 3000 Architecture Folding Interpolating SNR (dB) 57.2 ENOB (Bits) 8.9 SFDR (dB) 76 Operating temperature range (C) -55 to 125, 25 to 25 Input buffer Yes
Sample rate (Max) (MSPS) 3200, 6400 Resolution (Bits) 12 Number of input channels 2, 1 Interface type JESD204B Analog input BW (MHz) 7300 Features Ultra High Speed Rating Space Input range (Vp-p) 0.8 Power consumption (Typ) (mW) 3000 Architecture Folding Interpolating SNR (dB) 57.2 ENOB (Bits) 8.9 SFDR (dB) 76 Operating temperature range (C) -55 to 125, 25 to 25 Input buffer Yes
open-in-new Find other High-speed ADCs (>10MSPS)
CCGA (NWE) 196 225 mm² 15 x 15 CLGA (ZMX) 196 225 mm² 15 x 15
open-in-new Find other High-speed ADCs (>10MSPS)
  • ADC core:
    • 12-Bit resolution
    • Up to 6.4 GSPS in single-channel mode
    • Up to 3.2 GSPS in dual-channel mode
  • Noise floor (no signal, VFS = 1 VPP-DIFF):
    • Dual-channel mode: –149.5 dBFS/Hz
    • Single-channel mode: –152.4 dBFS/Hz
  • Peak noise power ratio (NPR): 45.4 dB
  • Buffered analog inputs with VCMI of 0 V:
    • Analog input bandwidth (–3 dB): 7 GHz
    • Usable input frequency range: >10 GHz
    • Full-scale input voltage (VFS, default): 0.8 VPP
  • Noiseless aperture delay (tAD) adjustment:
    • Precise sampling control: 19-fs step size
    • Temperature and voltage invariant delays
  • Easy-to-use synchronization features
    • Automatic SYSREF timing calibration
    • Timestamp for sample marking
  • JESD204B subclass-1 compliant interface:
    • Maximum lane rate: 12.8 Gbps
    • Up to 16 lanes allows reduced lane rate
  • Digital down-converters in dual-channel mode:
    • Real output: DDC bypass or 2x decimation
    • Complex output: 4x, 8x, or 16x decimation
  • Radiation performance:
    • Total Ionizing Dose (TID): 300 krad (Si)
    • Single Event Latchup (SEL): 120 MeV-cm2/mg
    • Single Event Upset (SEU) immune registers
  • Power consumption: 3 W
  • ADC core:
    • 12-Bit resolution
    • Up to 6.4 GSPS in single-channel mode
    • Up to 3.2 GSPS in dual-channel mode
  • Noise floor (no signal, VFS = 1 VPP-DIFF):
    • Dual-channel mode: –149.5 dBFS/Hz
    • Single-channel mode: –152.4 dBFS/Hz
  • Peak noise power ratio (NPR): 45.4 dB
  • Buffered analog inputs with VCMI of 0 V:
    • Analog input bandwidth (–3 dB): 7 GHz
    • Usable input frequency range: >10 GHz
    • Full-scale input voltage (VFS, default): 0.8 VPP
  • Noiseless aperture delay (tAD) adjustment:
    • Precise sampling control: 19-fs step size
    • Temperature and voltage invariant delays
  • Easy-to-use synchronization features
    • Automatic SYSREF timing calibration
    • Timestamp for sample marking
  • JESD204B subclass-1 compliant interface:
    • Maximum lane rate: 12.8 Gbps
    • Up to 16 lanes allows reduced lane rate
  • Digital down-converters in dual-channel mode:
    • Real output: DDC bypass or 2x decimation
    • Complex output: 4x, 8x, or 16x decimation
  • Radiation performance:
    • Total Ionizing Dose (TID): 300 krad (Si)
    • Single Event Latchup (SEL): 120 MeV-cm2/mg
    • Single Event Upset (SEU) immune registers
  • Power consumption: 3 W
open-in-new Find other High-speed ADCs (>10MSPS)

The ADC12DJ3200QML-SP device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from dc to above 10 GHz. In dual-channel mode, the ADC12DJ3200QML-SP can sample up to 3200 MSPS. In single-channel mode, the device can sample up to 6400 MSPS. Programmable tradeoffs in channel count (dual-channel mode) and Nyquist bandwidth (single-channel mode) allow development of flexible hardware that meets the needs of both high channel count or wide instantaneous signal bandwidth applications. Full-power input bandwidth (–3 dB) of 7 GHz, with usable frequencies exceeding the –3-dB point in both dual- and single-channel modes, allows direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.

The ADC12DJ3200QML-SP uses a high-speed JESD204B output interface with up to 16 serialized lanes and subclass-1 compliance for deterministic latency and multidevice synchronization. The serial output lanes support up to 12.8 Gbps, and can be configured to trade off bit rate and number of lanes. Innovative synchronization features, including noiseless aperture delay (tAD) adjustment and SYSREF windowing, simplify system design for synthetic aperture radar (SAR) and phased-array MIMO communications. Optional digital down converters (DDCs) in dual-channel mode allow for reduction in interface rate (real and complex decimation modes) and digital mixing of the signal (complex decimation modes only).

The ADC12DJ3200QML-SP device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from dc to above 10 GHz. In dual-channel mode, the ADC12DJ3200QML-SP can sample up to 3200 MSPS. In single-channel mode, the device can sample up to 6400 MSPS. Programmable tradeoffs in channel count (dual-channel mode) and Nyquist bandwidth (single-channel mode) allow development of flexible hardware that meets the needs of both high channel count or wide instantaneous signal bandwidth applications. Full-power input bandwidth (–3 dB) of 7 GHz, with usable frequencies exceeding the –3-dB point in both dual- and single-channel modes, allows direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.

The ADC12DJ3200QML-SP uses a high-speed JESD204B output interface with up to 16 serialized lanes and subclass-1 compliance for deterministic latency and multidevice synchronization. The serial output lanes support up to 12.8 Gbps, and can be configured to trade off bit rate and number of lanes. Innovative synchronization features, including noiseless aperture delay (tAD) adjustment and SYSREF windowing, simplify system design for synthetic aperture radar (SAR) and phased-array MIMO communications. Optional digital down converters (DDCs) in dual-channel mode allow for reduction in interface rate (real and complex decimation modes) and digital mixing of the signal (complex decimation modes only).

open-in-new Find other High-speed ADCs (>10MSPS)
Download

Technical documentation

star = Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 13
Type Title Date
* Data sheet ADC12DJ3200QML-SP 6.4-GSPS, Single-Channel or 3.2-GSPS, Dual-Channel, 12-Bit, RF-Sampling Analog-to-Digital Converter (ADC) datasheet (Rev. B) 24 Mar 2021
* SMD ADC12DJ3200QML-SP SMD ADC12DJ3200QML-SP SMD 5962-18209 04 Aug 2020
* Radiation & reliability report ADC12DJ3200QML-SP - Single-Event Effects (SEE) Radiation Test Report 03 Aug 2020
* Radiation & reliability report Analysis of Low Dose Rate Effects on Parasitic Bipolar Structures in CMOS Proces 04 May 2012
Technical article How smart AFEs offer an integrated analog solution for thermoelectric cooling control 04 Jan 2022
Selection guide TI Space Products (Rev. H) 27 Jan 2021
Technical article Keys to quick success using high-speed data converters 13 Oct 2020
Application note Heavy Ion Orbital Environment Single-Event Effects Estimations 18 May 2020
Application note Single-Event Effects Confidence Interval Calculations 14 Jan 2020
More literature TI Engineering Evaluation Units vs. MIL-PRF-38535 QML Class V Processing 17 Jun 2019
Technical article How to achieve fast frequency hopping 03 Mar 2019
User guide ADC12DJ3200EVMCVAL Evaluation Module User's Guide 11 Jan 2018
Technical article RF sampling: Learning more about latency 09 Feb 2017

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

ADC12DJ3200EVM — ADC12DJ3200 12-bit, dual 3.2-GSPS or single 6.4-GSPS, RF-sampling ADC evaluation module

The ADC12DJ3200 evaluation module (EVM) allows for the evaluation of device ADC12DJ3200. The ADC12DJ3200 is a low-power, 12-bit, dual 3.2-GSPS/single 6.4-GSPS, RF-sampling analog-to-digital converter (ADC) with a buffered analog input, integrated digital down converter with programmable NCO and (...)

document-pdfAcrobat User guide
In stock
Limit: 9
Evaluation board

ADC12DJ3200EVMCVAL — ADC12DJ3200QML-SP 12-bit, dual 3.2-GSPS or single 6.4-GSPS, RF-sampling ADC space evaluation module

The ADC12DJ3200EVMCVAL is an evaluation module (EVM) that evaluates the ADC12DJ3200QML-SP device. ADC12DJ3200QML-SP is a space-grade, low-power, 12-bit, dual 3.2-GSPS/single 6.4-GSPS, RF-sampling analog-to-digital converter (ADC) with a buffered analog input, integrated digital down converter, (...)

document-pdfAcrobat User guide
In stock
Limit: 5
Firmware

TI-JESD204-IP — JESD204 Rapid Design IP for FPGAs connected to TI high-speed data converters

The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
Request
Support software

Xilinx AlphaData Demo (Rev. A)

SLVC806A.ZIP (5958 KB)
Download
Simulation model

ADC12DJ3200QML-SP IBIS Model

SLVMDP0.ZIP (145 KB) - IBIS Model
Download
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Request
Assembly drawing

ADC12DJ3200QML-EVM Assembly Package

SLVRBF5.ZIP (4838 KB)
Download
Gerber file

ADC12DJ3200EVMCVAL Design Files

SLVC819.ZIP (4838 KB)
Download
Package Pins Download
CCGA (NWE) 196 View options
CLGA (ZMX) 196 View options

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Support & training

TI E2E™ forums with technical support from TI engineers

View all forum topics

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos