SLVSDR2C November   2018  â€“ March 2025 ADC12DJ3200QML-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics: DC Specifications
    6. 5.6  Electrical Characteristics: Power Consumption
    7. 5.7  Electrical Characteristics: AC Specifications (Dual-Channel Mode)
    8. 5.8  Electrical Characteristics: AC Specifications (Single-Channel Mode)
    9. 5.9  Timing Requirements
    10. 5.10 Switching Characteristics
    11. 5.11 Timing Diagrams
    12. 5.12 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Analog Inputs
        1. 6.3.1.1 Analog Input Protection
        2. 6.3.1.2 Full-Scale Voltage (VFS) Adjustment
        3. 6.3.1.3 Analog Input Offset Adjust
      2. 6.3.2 ADC Core
        1. 6.3.2.1 ADC Theory of Operation
        2. 6.3.2.2 ADC Core Calibration
        3. 6.3.2.3 ADC Overrange Detection
        4. 6.3.2.4 Code Error Rate (CER)
      3. 6.3.3 Timestamp
      4. 6.3.4 Clocking
        1. 6.3.4.1 Noiseless Aperture Delay Adjustment (tAD Adjust)
        2. 6.3.4.2 Aperture Delay Ramp Control (TAD_RAMP)
        3. 6.3.4.3 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
          1. 6.3.4.3.1 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
          2. 6.3.4.3.2 Automatic SYSREF Calibration
      5. 6.3.5 Digital Down Converters (Dual-Channel Mode Only)
        1. 6.3.5.1 Numerically-Controlled Oscillator and Complex Mixer
          1. 6.3.5.1.1 NCO Fast Frequency Hopping (FFH)
          2. 6.3.5.1.2 NCO Selection
          3. 6.3.5.1.3 Basic NCO Frequency Setting Mode
          4. 6.3.5.1.4 Rational NCO Frequency Setting Mode
          5. 6.3.5.1.5 NCO Phase Offset Setting
          6. 6.3.5.1.6 NCO Phase Synchronization
        2. 6.3.5.2 Decimation Filters
        3. 6.3.5.3 Output Data Format
        4. 6.3.5.4 Decimation Settings
          1. 6.3.5.4.1 Decimation Factor
          2. 6.3.5.4.2 DDC Gain Boost
      6. 6.3.6 JESD204B Interface
        1. 6.3.6.1 Transport Layer
        2. 6.3.6.2 Scrambler
        3. 6.3.6.3 Link Layer
          1. 6.3.6.3.1 Code Group Synchronization (CGS)
          2. 6.3.6.3.2 Initial Lane Alignment Sequence (ILAS)
          3. 6.3.6.3.3 8b, 10b Encoding
          4. 6.3.6.3.4 Frame and Multiframe Monitoring
        4. 6.3.6.4 Physical Layer
          1. 6.3.6.4.1 SerDes Pre-Emphasis
        5. 6.3.6.5 JESD204B Enable
        6. 6.3.6.6 Multi-Device Synchronization and Deterministic Latency
        7. 6.3.6.7 Operation in Subclass 0 Systems
      7. 6.3.7 Alarm Monitoring
        1. 6.3.7.1 NCO Upset Detection
        2. 6.3.7.2 Clock Upset Detection
      8. 6.3.8 Temperature Monitoring Diode
      9. 6.3.9 Analog Reference Voltage
    4. 6.4 Device Functional Modes
      1. 6.4.1 Dual-Channel Mode
      2. 6.4.2 Single-Channel Mode (DES Mode)
      3. 6.4.3 JESD204B Modes
        1. 6.4.3.1 JESD204B Output Data Formats
        2. 6.4.3.2 Dual DDC and Redundant Data Mode
      4. 6.4.4 Power-Down Modes
      5. 6.4.5 Test Modes
        1. 6.4.5.1 Serializer Test-Mode Details
        2. 6.4.5.2 PRBS Test Modes
        3. 6.4.5.3 Ramp Test Mode
        4. 6.4.5.4 Short and Long Transport Test Mode
          1. 6.4.5.4.1 Short Transport Test Pattern
          2. 6.4.5.4.2 Long Transport Test Pattern
        5. 6.4.5.5 D21.5 Test Mode
        6. 6.4.5.6 K28.5 Test Mode
        7. 6.4.5.7 Repeated ILA Test Mode
        8. 6.4.5.8 Modified RPAT Test Mode
      6. 6.4.6 Calibration Modes and Trimming
        1. 6.4.6.1 Foreground Calibration Mode
        2. 6.4.6.2 Background Calibration Mode
        3. 6.4.6.3 Low-Power Background Calibration (LPBG) Mode
      7. 6.4.7 Offset Calibration
      8. 6.4.8 Trimming
      9. 6.4.9 Offset Filtering
    5. 6.5 Programming
      1. 6.5.1 Using the Serial Interface
        1. 6.5.1.1 SCS
        2. 6.5.1.2 SCLK
        3. 6.5.1.3 SDI
        4. 6.5.1.4 SDO
        5. 6.5.1.5 Streaming Mode
    6. 6.6 Register Maps
      1. 6.6.1 Register Descriptions
      2. 6.6.2 SYSREF Calibration Registers (0x2B0 to 0x2BF)
      3. 6.6.3 Alarm Registers (0x2C0 to 0x2C2)
  8. 7 Application Information Disclaimer
    1. 7.1 Application Information
      1. 7.1.1 Analog Inputs
      2. 7.1.2 Analog Input Bandwidth
      3. 7.1.3 Clocking
      4. 7.1.4 Radiation Environment Recommendations
        1. 7.1.4.1 Single Event Latch-Up (SEL)
        2. 7.1.4.2 Single Event Functional Interrupt (SEFI)
        3. 7.1.4.3 Single Event Upset (SEU)
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 RF Input Signal Path
        2. 7.2.2.2 Calculating Values of AC-Coupling Capacitors
      3. 7.2.3 Application Curves
    3. 7.3 Initialization Set Up
    4.     Power Supply Recommendations
      1. 7.4.1 Power Sequencing
    5. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Third-Party Products Disclaimer
    4. 8.4 Receiving Notification of Documentation Updates
    5. 8.5 Support Resources
    6. 8.6 Trademarks
    7. 8.7 Electrostatic Discharge Caution
    8. 8.8 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Abstract

The device requires two different power-supply voltages. 1.9V DC is required for the VA19 power bus and 1.1V DC is required for the VA11 and VD11 power buses. The power-supply voltages must be low noise and provide the needed current to achieve rated device performance.

There are two recommended power supply architectures:

  1. Step down from the system voltage using high-efficiency DC/DC switching converters followed by a second stage of low-noise regulation by a low drop-out linear regulator (LDO). The LDO provides switching noise reduction, reduces passive filtering requirements and improves voltage accuracy if placed locally at the ADC.
  2. Directly step down from the system voltage to the final ADC supply voltages using high-efficiency DC/DC switching converters. This approach provides the best efficiency, but care must be taken to make sure switching noise is minimized to prevent degraded ADC performance. Additional passive filtering is required for best performance, and any series components may reduce the actual voltage at the ADC.

TI WEBENCH® Power Designer can be used to select and design the individual power supply elements needed: see the WEBENCH® Power Designer.

A recommended DC/DC switching regulator for the first stage is the TPS50601A-SP, but other similar devices can be used as well. Recommended LDOs for the second stage include TPS7H1101A-SP, TPS7A4501-SP and other similar devices.

For the switcher only approach, the ripple filter must be designed to provide sufficient filtering at the switching frequency of the DC-DC converter and harmonics. WEBENCH® reports the switching frequency when used to design the supply. Each application will have different tolerances for noise on the supply voltage so strict ripple requirements are not provided. Figure 7-6 and Figure 7-7 illustrate the two approaches.

ADC12DJ3200QML-SP LDO Linear Regulator ExampleFigure 7-6 LDO Linear Regulator Example
ADC12DJ3200QML-SP DC/DC Switching Regulator ExampleFigure 7-7 DC/DC Switching Regulator Example