SLVSDR9F October   2016  – June 2026 DRV8702-Q1 , DRV8703-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1.     Pin Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 SPI Timing Requirements
    7. 5.7 Switching Characteristics
    8.     15
    9. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Bridge Control
        1. 6.3.1.1 Logic Tables
      2. 6.3.2  MODE Pin
      3. 6.3.3  nFAULT Pin
      4. 6.3.4  Current Regulation
      5. 6.3.5  Amplifier Output (SO)
        1. 6.3.5.1 SO Sample and Hold Operation
      6. 6.3.6  PWM Motor Gate Drivers
        1. 6.3.6.1 Miller Charge (QGD)
      7. 6.3.7  IDRIVE Pin (DRV8702-Q1 Only)
      8. 6.3.8  Dead Time
      9. 6.3.9  Propagation Delay
      10. 6.3.10 Overcurrent VDS Monitor
      11. 6.3.11 VDS Pin (DRV8702-Q1 Only)
      12. 6.3.12 Charge Pump
      13. 6.3.13 Gate Drive Clamp
      14. 6.3.14 Protection Circuits
        1. 6.3.14.1 VM Undervoltage Lockout (UVLO2)
        2. 6.3.14.2 Logic Undervoltage (UVLO1)
        3. 6.3.14.3 VCP Undervoltage Lockout (CPUV)
        4. 6.3.14.4 Overcurrent Protection (OCP)
        5. 6.3.14.5 Gate Driver Fault (GDF)
        6. 6.3.14.6 Thermal Shutdown (TSD)
        7. 6.3.14.7 Watchdog Fault (WDFLT, DRV8703-Q1 Only)
        8. 6.3.14.8 Reverse Supply Protection
      15. 6.3.15 Hardware Interface
        1. 6.3.15.1 IDRIVE (6-level input)
        2. 6.3.15.2 VDS (6-Level Input)
    4. 6.4 Device Functional Modes
    5. 6.5 Programming
      1. 6.5.1 SPI Communication
        1. 6.5.1.1 Serial Peripheral Interface (SPI)
        2. 6.5.1.2 SPI Format
  8. 7 Register Maps
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 External FET Selection
        2. 8.2.2.2 IDRIVE Configuration
        3. 8.2.2.3 VDS Configuration
        4. 8.2.2.4 Current Chopping Configuration
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance Sizing
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

6.3.4 Current Regulation

The maximum current through the motor winding is regulated by a fixed off-time PWM current regulation or current chopping. When an H-bridge is enabled in forward or reverse drive, current rises through the winding at a rate dependent on the DC voltage and inductance of the winding. When the current hits the current chopping threshold, the bridge enters a brake (low-side slow decay) mode until the toff time expires.

Note:

Immediately after the current is enabled, the voltage on the SP pin is ignored for a period (t(BLANK)) before enabling the current-sense circuitry.

The PWM chopping current is set by a comparator that compares the voltage across a current-sense resistor connected to the SP pin, multiplied by a factor of AV, with a reference voltage from the VREF pin. The factor AV is the shunt-amplifier gain, which is 19.8V/V for the DRV8702-Q1 device or configurable to 10, 19.8, 39.4, or 7 V/V for the DRV8703-Q1 device.

Use Equation 1 to calculate the chopping current (ICHOP).

Equation 1. DRV8702-Q1 DRV8703-Q1

For example, if a 50mΩ sense resistor and a VREF value of 3.3V are selected, the full-scale chopping current is 3.28A. The AV is 19.8V/V and VIO is assumed to be 50mV in this example.

For DC motors, current regulation is used to limit the start-up and stall current of the motor. If the current regulation feature is not needed, the current regulation feature can be disabled by tying the VREF pin directly to the AVDD pin. If the independent PWM control-interface mode (MODE pin is 1) is selected for operation, the device does not perform PWM current regulation or current chopping.