SLVSF16B January   2021  – April 2022 DRV8316

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 SPI Timing Requirements
    7. 7.7 SPI Slave Mode Timings
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Output Stage
      2. 8.3.2  Control Modes
        1. 8.3.2.1 6x PWM Mode (MODE = 00b or MODE Pin Tied to AGND)
        2. 8.3.2.2 3x PWM Mode (MODE = 10b or MODE Pin is Connected to AGND with RMODE)
        3. 8.3.2.3 Current Limit Mode (MODE = 01b / 11b or MODE Pin is Hi-Z or Connected to AVDD)
      3. 8.3.3  Device Interface Modes
        1. 8.3.3.1 Serial Peripheral Interface (SPI)
        2. 8.3.3.2 Hardware Interface
      4. 8.3.4  Step-Down Mixed-Mode Buck Regulator
        1. 8.3.4.1 Buck in Inductor Mode
        2. 8.3.4.2 Buck in Resistor mode
        3. 8.3.4.3 Buck Regulator with External LDO
        4. 8.3.4.4 AVDD Power Sequencing on Buck Regulator
        5. 8.3.4.5 Mixed mode Buck Operation and Control
      5. 8.3.5  AVDD Linear Voltage Regulator
      6. 8.3.6  Charge Pump
      7. 8.3.7  Slew Rate Control
      8. 8.3.8  Cross Conduction (Dead Time)
      9. 8.3.9  Propagation Delay
        1. 8.3.9.1 Driver Delay Compensation
      10. 8.3.10 Pin Diagrams
        1. 8.3.10.1 Logic Level Input Pin (Internal Pulldown)
        2. 8.3.10.2 Logic Level Input Pin (Internal Pullup)
        3. 8.3.10.3 Open Drain Pin
        4. 8.3.10.4 Push Pull Pin
        5. 8.3.10.5 Four Level Input Pin
      11. 8.3.11 Current Sense Amplifiers
        1. 8.3.11.1 Current Sense Amplifier Operation
        2. 8.3.11.2 Current Sense Amplifier Offset Correction
      12. 8.3.12 Active Demagnetization
        1. 8.3.12.1 Automatic Synchronous Rectification Mode (ASR Mode)
          1. 8.3.12.1.1 Automatic Synchronous Rectification in Commutation
          2. 8.3.12.1.2 Automatic Synchronous Rectification in PWM Mode
        2. 8.3.12.2 Automatic Asynchronous Rectification Mode (AAR Mode)
      13. 8.3.13 Cycle-by-Cycle Current Limit
        1. 8.3.13.1 Cycle by Cycle Current Limit with 100% Duty Cycle Input
      14. 8.3.14 Protections
        1. 8.3.14.1 VM Supply Undervoltage Lockout (NPOR)
        2. 8.3.14.2 AVDD Undervoltage Lockout (AVDD_UV)
        3. 8.3.14.3 BUCK Undervoltage Lockout (BUCK_UV)
        4. 8.3.14.4 VCP Charge Pump Undervoltage Lockout (CPUV)
        5. 8.3.14.5 Overvoltage Protections (OV)
        6. 8.3.14.6 Overcurrent Protection (OCP)
          1. 8.3.14.6.1 OCP Latched Shutdown (OCP_MODE = 00b)
          2. 8.3.14.6.2 OCP Automatic Retry (OCP_MODE = 01b)
          3. 8.3.14.6.3 OCP Report Only (OCP_MODE = 10b)
          4. 8.3.14.6.4 OCP Disabled (OCP_MODE = 11b)
        7. 8.3.14.7 Buck Overcurrent Protection
        8. 8.3.14.8 Thermal Warning (OTW)
        9. 8.3.14.9 Thermal Shutdown (OTS)
          1. 8.3.14.9.1 OTS FET
          2. 8.3.14.9.2 OTS (Non FET)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Functional Modes
        1. 8.4.1.1 Sleep Mode
        2. 8.4.1.2 Operating Mode
        3. 8.4.1.3 Fault Reset (CLR_FLT or nSLEEP Reset Pulse)
      2. 8.4.2 DRVOFF functionality
    5. 8.5 SPI Communication
      1. 8.5.1 Programming
        1. 8.5.1.1 SPI Format
    6. 8.6 Register Map
      1. 8.6.1 STATUS Registers
      2. 8.6.2 CONTROL Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Three-Phase Brushless-DC Motor Control
        1. 9.2.1.1 Detailed Design Procedure
          1. 9.2.1.1.1 Motor Voltage
          2. 9.2.1.1.2 Using Active Demagnetization
          3. 9.2.1.1.3 Driver Propagation Delay and Dead Time
          4. 9.2.1.1.4 Using Delay Compensation
          5. 9.2.1.1.5 Using the Buck Regulator
          6. 9.2.1.1.6 Current Sensing and Output Filtering
          7. 9.2.1.1.7 Power Dissipation and Junction Temperature Losses
        2. 9.2.1.2 Application Curves
      2. 9.2.2 Three-Phase Brushless-DC Motor Control With Current Limit
        1. 9.2.2.1 Block Diagram
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Motor Voltage
          2. 9.2.2.2.2 ILIM Implementation
        3. 9.2.2.3 Application Curves
      3. 9.2.3 Brushed-DC and Solenoid Load
        1. 9.2.3.1 Block Diagram
        2. 9.2.3.2 Design Requirements
          1. 9.2.3.2.1 Detailed Design Procedure
      4. 9.2.4 Three Solenoid Loads
        1. 9.2.4.1 Block Diagram
        2. 9.2.4.2 Design Requirements
          1. 9.2.4.2.1 Detailed Design Procedure
  10. 10Power Supply Recommendations
    1. 10.1 Bulk Capacitance
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
      1. 11.3.1 Power Dissipation
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

8.6.2 CONTROL Registers

#CONTROL_CONTROL_TABLE_1 lists the memory-mapped registers for the CONTROL registers. All register offset addresses not listed in #CONTROL_CONTROL_TABLE_1 should be considered as reserved locations and the register contents should not be modified.

Table 8-16 CONTROL Registers
Offset Acronym Register Name Section
3h Control_Register_1 Control Register 1 #CONTROL_CONTROL_CONTROL_CTRL1
4h Control_Register_2 Control Register 2 #CONTROL_CONTROL_CONTROL_CTRL2
5h Control_Register_3 Control Register 3 #CONTROL_CONTROL_CONTROL_CTRL3
6h Control_Register_4 Control Register 4 #CONTROL_CONTROL_CONTROL_CTRL4
7h Control_Register_5 Control Register 5 #CONTROL_CONTROL_CONTROL_CTRL5
8h Control_Register_6 Control Register 6 #CONTROL_CONTROL_CONTROL_CTRL6
Ch Control_Register_10 Control Register 10 #CONTROL_CONTROL_CONTROL_CTRL10

Complex bit access types are encoded to fit into small table cells. #CONTROL_CONTROL_LEGEND shows the codes that are used for access types in this section.

Table 8-17 CONTROL Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R
-0		 Read
Returns 0s
Write Type
W W Write
W1C W
1C		 Write
1 to clear
WAPU W
APU		 Write
Atomic write with password unlock
Reset or Default Value
-n Value after reset or the default value

8.6.2.1 Control_Register_1 Register (Offset = 3h) [Reset = 00h]

Control_Register_1 is shown in #CONTROL_CONTROL_CONTROL_CTRL1_FIGURE and described in #CONTROL_CONTROL_CONTROL_CTRL1_TABLE.

Return to the Summary Table.

Figure 8-50 Control_Register_1 Register
7 6 5 4 3 2 1 0
RESERVED REG_LOCK
R-0-0h R/WAPU-0h
Table 8-18 Control_Register_1 Register Field Descriptions
Bit Field Type Reset Description
7-3 RESERVED R-0 0h Reserved
2-0 REG_LOCK R/WAPU 0h Register Lock Bits

0h = No effect unless locked or unlocked

1h = No effect unless locked or unlocked

2h = No effect unless locked or unlocked

3h = Write 011b to this register to unlock all registers

4h = No effect unless locked or unlocked

5h = No effect unless locked or unlocked

6h = Write 110b to lock the settings by ignoring further register writes except to these bits and address 0x03h bits 2-0.

7h = No effect unless locked or unlocked

8.6.2.2 Control_Register_2 Register (Offset = 4h) [Reset = 60h]

Control_Register_2 is shown in #CONTROL_CONTROL_CONTROL_CTRL2_FIGURE and described in #CONTROL_CONTROL_CONTROL_CTRL2_TABLE.

Return to the Summary Table.

Figure 8-51 Control_Register_2 Register
7 6 5 4 3 2 1 0
RESERVED SDO_MODE SLEW PWM_MODE CLR_FLT
R/W-1h R/W-1h R/W-0h R/W-0h W1C-0h
Table 8-19 Control_Register_2 Register Field Descriptions
Bit Field Type Reset Description
7-6 RESERVED R/W 1h Reserved
5 SDO_MODE R/W 1h SDO Mode Setting

0h = SDO IO in Open Drain Mode

1h = SDO IO in Push Pull Mode

4-3 SLEW R/W 0h Slew Rate Settings

0h = Slew rate is 25 V/µs

1h = Slew rate is 50 V/µs

2h = Slew rate is 125 V/µs

3h = Slew rate is 200 V/µs

2-1 PWM_MODE R/W 0h Device Mode Selection

0h = 6x mode

1h = 6x mode with current limit

2h = 3x mode

3h = 3x mode with current limit

0 CLR_FLT W1C 0h Clear Fault

0h = No clear fault command is issued

1h = To clear the latched fault bits. This bit automatically resets after being written.

8.6.2.3 Control_Register_3 Register (Offset = 5h) [Reset = 46h]

Control_Register_3 is shown in #CONTROL_CONTROL_CONTROL_CTRL3_FIGURE and described in #CONTROL_CONTROL_CONTROL_CTRL3_TABLE.

Return to the Summary Table.

Figure 8-52 Control_Register_3 Register
7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED PWM_100_DUTY_SEL OVP_SEL OVP_EN RESERVED OTW_REP
R-0-0h R/W-1h R/W-0h R/W-0h R/W-0h R/W-1h R/W-1h R/W-0h
Table 8-20 Control_Register_3 Register Field Descriptions
Bit Field Type Reset Description
7 RESERVED R-0 0h Reserved
6 RESERVED R/W 1h Reserved
5 RESERVED R/W 0h Reserved
4 PWM_100_DUTY_SEL R/W 0h Freqency of PWM at 100% Duty Cycle

0h = 20KHz

1h = 40KHz

3 OVP_SEL R/W 0h Overvoltage Level Setting

0h = VM overvoltage level is 34-V

1h = VM overvoltage level is 22-V

2 OVP_EN R/W 1h Overvoltage Enable Bit

0h = Overvoltage protection is disabled

1h = Overvoltage protection is enabled

1 RESERVED R/W 1h Reserved
0 OTW_REP R/W 0h Overtemperature Warning Reporting Bit

0h = Over temperature reporting on nFAULT is disabled

1h = Over temperature reporting on nFAULT is enabled

8.6.2.4 Control_Register_4 Register (Offset = 6h) [Reset = 10h]

Control_Register_4 is shown in #CONTROL_CONTROL_CONTROL_CTRL4_FIGURE and described in #CONTROL_CONTROL_CONTROL_CTRL4_TABLE.

Return to the Summary Table.

Figure 8-53 Control_Register_4 Register
7 6 5 4 3 2 1 0
DRV_OFF OCP_CBC OCP_DEG OCP_RETRY OCP_LVL OCP_MODE
R/W-0h R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h
Table 8-21 Control_Register_4 Register Field Descriptions
Bit Field Type Reset Description
7 DRV_OFF R/W 0h Driver OFF Bit

0h = No Action

1h = Enter Low Power Standby Mode

6 OCP_CBC R/W 0h OCP PWM Cycle Operation Bit

0h = OCP clearing in PWM input cycle change is disabled

1h = OCP clearing in PWM input cycle change is enabled

5-4 OCP_DEG R/W 1h OCP Deglitch Time Settings

0h = OCP deglitch time is 0.2 µs

1h = OCP deglitch time is 0.6 µs

2h = OCP deglitch time is 1.25 µs

3h = OCP deglitch time is 1.6 µs

3 OCP_RETRY R/W 0h OCP Retry Time Settings

0h = OCP retry time is 5 ms

1h = OCP retry time is 500 ms

2 OCP_LVL R/W 0h Overcurrent Level Setting

0h = OCP level is 16 A

1h = OCP level is 24 A

1-0 OCP_MODE R/W 0h OCP Fault Options

0h = Overcurrent causes a latched fault

1h = Overcurrent causes an automatic retrying fault

2h = Overcurrent is report only but no action is taken

3h = Overcurrent is not reported and no action is taken

8.6.2.5 Control_Register_5 Register (Offset = 7h) [Reset = 00h]

Control_Register_5 is shown in #CONTROL_CONTROL_CONTROL_CTRL5_FIGURE and described in #CONTROL_CONTROL_CONTROL_CTRL5_TABLE.

Return to the Summary Table.

Figure 8-54 Control_Register_5 Register
7 6 5 4 3 2 1 0
RESERVED ILIM_RECIR RESERVED RESERVED EN_AAR EN_ASR CSA_GAIN
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
Table 8-22 Control_Register_5 Register Field Descriptions
Bit Field Type Reset Description
7 RESERVED R/W 0h Reserved
6 ILIM_RECIR R/W 0h Current Limit Recirculation Settings

0h = Current recirculation through FETs (Brake Mode)

1h = Current recirculation through diodes (Coast Mode)

5 RESERVED R/W 0h Reserved
4 RESERVED R/W 0h Reserved
3 EN_AAR R/W 0h Active Asynshronous Rectification Enable Bit

0h = AAR mode is disabled

1h = AAR mode is enabled

2 EN_ASR R/W 0h Active Synchronous Rectification Enable Bit

0h = ASR mode is disabled

1h = ASR mode is enabled

1-0 CSA_GAIN R/W 0h Current Sense Amplifier's Gain Settings

0h = CSA gain is 0.15 V/A

1h = CSA gain is 0.3 V/A

2h = CSA gain is 0.6 V/A

3h = CSA gain is 1.2 V/A

8.6.2.6 Control_Register_6 Register (Offset = 8h) [Reset = 00h]

Control_Register_6 is shown in #CONTROL_CONTROL_CONTROL_CTRL6_FIGURE and described in #CONTROL_CONTROL_CONTROL_CTRL6_TABLE.

Return to the Summary Table.

Figure 8-55 Control_Register_6 Register
7 6 5 4 3 2 1 0
RESERVED RESERVED BUCK_PS_DIS BUCK_CL BUCK_SEL BUCK_DIS
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
Table 8-23 Control_Register_6 Register Field Descriptions
Bit Field Type Reset Description
7-6 RESERVED R-0 0h Reserved
5 RESERVED R/W 0h Reserved
4 BUCK_PS_DIS R/W 0h Buck Power Sequencing Disable Bit

0h = Buck power sequencing is enabled

1h = Buck power sequencing is disabled

3 BUCK_CL R/W 0h Buck Current Limit Setting

0h = Buck regulator current limit is set to 600 mA

1h = Buck regulator current limit is set to 150 mA

2-1 BUCK_SEL R/W 0h Buck Voltage Selection

0h = Buck voltage is 3.3 V

1h = Buck voltage is 5.0 V

2h = Buck voltage is 4.0 V

3h = Buck voltage is 5.7 V

0 BUCK_DIS R/W 0h Buck Disable Bit

0h = Buck regulator is enabled

1h = Buck regulator is disabled

8.6.2.7 Control_Register_10 Register (Offset = Ch) [Reset = 00h]

Control_Register_10 is shown in #CONTROL_CONTROL_CONTROL_CTRL10_FIGURE and described in #CONTROL_CONTROL_CONTROL_CTRL10_TABLE.

Return to the Summary Table.

Figure 8-56 Control_Register_10 Register
7 6 5 4 3 2 1 0
RESERVED DLYCMP_EN DLY_TARGET
R-0-0h R/W-0h R/W-0h
Table 8-24 Control_Register_10 Register Field Descriptions
Bit Field Type Reset Description
7-5 RESERVED R-0 0h Reserved
4 DLYCMP_EN R/W 0h Driver Delay Compensation enable

0h = Disable

1h = Enable

3-0 DLY_TARGET R/W 0h Delay Target for Driver Delay Compensation

0h = 0 us

1h = 0.4 us

2h = 0.6 us

3h = 0.8 us

4h = 1 us

5h = 1.2 us

6h = 1.4 us

7h = 1.6 us

8h = 1.8 us

9h = 2 us

Ah = 2.2 us

Bh = 2.4 us

Ch = 2.6 us

Dh = 2.8 us

Eh = 3 us

Fh = 3.2 us