SLVSFV5C July   2023  – July 2025 DRV8262

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
      1. 5.4.1 Transient Thermal Impedance & Current Capability
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1  Overview
    2. 6.2  Functional Block Diagram
    3. 6.3  Feature Description
      1. 6.3.1 Spread Spectrum
    4. 6.4  Device Operational Modes
      1. 6.4.1 Dual H-Bridge Mode (MODE1 = 0)
      2. 6.4.2 Single H-Bridge Mode (MODE1 = 1)
    5. 6.5  Current Sensing and Regulation
      1. 6.5.1 Current Sensing and Feedback
      2. 6.5.2 Current Regulation
        1. 6.5.2.1 Mixed Decay
        2. 6.5.2.2 Smart tune Dynamic Decay
      3. 6.5.3 Current Sensing with External Resistor
    6. 6.6  Charge Pump
    7. 6.7  Linear Voltage Regulator
    8. 6.8  VCC Voltage Supply
    9. 6.9  Logic Level, Tri-Level and Quad-Level Pin Diagrams
    10. 6.10 Protection Circuits
      1. 6.10.1 VM Undervoltage Lockout (UVLO)
      2. 6.10.2 VCP Undervoltage Lockout (CPUV)
      3. 6.10.3 Logic Supply Power on Reset (POR)
      4. 6.10.4 Overcurrent Protection (OCP)
      5. 6.10.5 Thermal Shutdown (OTSD)
      6. 6.10.6 nFAULT Output
      7. 6.10.7 Fault Condition Summary
    11. 6.11 Device Functional Modes
      1. 6.11.1 Sleep Mode
      2. 6.11.2 Operating Mode
      3. 6.11.3 nSLEEP Reset Pulse
      4. 6.11.4 Functional Modes Summary
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Driving Brushed-DC Motors
        1. 7.1.1.1 Brushed-DC Motor Driver Typical Application
        2. 7.1.1.2 Power Loss Calculations - Dual H-bridge
        3. 7.1.1.3 Power Loss Calculations - Single H-bridge
        4. 7.1.1.4 Junction Temperature Estimation
        5. 7.1.1.5 Application Performance Plots
      2. 7.1.2 Driving Stepper Motors
        1. 7.1.2.1 Stepper Driver Typical Application
        2. 7.1.2.2 Power Loss Calculations
        3. 7.1.2.3 Junction Temperature Estimation
      3. 7.1.3 Driving Thermoelectric Coolers (TEC)
    2. 7.2 Power Supply Recommendations
      1. 7.2.1 Bulk Capacitance
      2. 7.2.2 Power Supplies
    3. 7.3 Layout
      1. 7.3.1 Layout Guidelines
      2. 7.3.2 Layout Example
  9. 8 Package Thermal Considerations
    1. 8.1 DDW Package
      1. 8.1.1 Thermal Performance
        1. 8.1.1.1 Steady-State Thermal Performance
        2. 8.1.1.2 Transient Thermal Performance
    2. 8.2 DDV Package
    3. 8.3 PCB Material Recommendation
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

8.1.1 Thermal Performance

The data sheet-specified junction-to-ambient thermal resistance, RθJA, is primarily useful for comparing various drivers or approximating thermal performance. However, the actual system performance is better or worse than this value depending on PCB stack-up, routing, number of vias, and copper area around the thermal pad. The length of time the driver drives a particular current also impacts power dissipation and thermal performance. This section considers how to design for steady-state and transient thermal conditions.

The data in this section is simulated using the following criteria:

HTSSOP (DDW package)

  • 2-layer PCB (size 114.3 x 76.2 x 1.6mm), standard FR4, 1oz (35mm copper thickness) or 2oz copper thickness. Thermal vias are only present under the thermal pad (13 x 5 thermal via array, 1.1mm pitch, 0.2mm diameter, 0.025mm Cu plating).
    • Top layer: HTSSOP package footprint and copper plane heat sink. Top layer copper area is varied in simulation.
    • Bottom layer: ground plane thermally connected through vias under the thermal pad for the driver. Bottom layer copper area varies with top copper area.
  • 4-layer PCB (size 114.3 x 76.2 x 1.6mm), standard FR4. Outer planes are 1oz (35mm copper thickness) or 2oz copper thickness. Inner planes are kept at 1oz. Thermal vias are only present under the thermal pad (13 x 5 thermal via array, 1.1mm pitch, 0.2mm diameter, 0.025mm Cu plating).
    • Top layer: HTSSOP package footprint and copper plane heat sink. Top layer copper area is varied in simulation.
    • Mid layer 1: GND plane thermally connected to thermal pad through vias. The area of the ground plane varies with top copper area.
    • Mid layer 2: power plane, no thermal connection. The area of the power plane varies with top copper area.
    • Bottom layer: signal layer thermally connected through via stitching from the TOP and internal GND plane. Bottom layer thermal pad is the same size as the top layer copper area.

Figure 8-1 shows an example of the simulated board for the DDW package. Table 8-1 shows the dimensions of the board that are varied for each simulation.

DRV8262 DDW PCB model top layerFigure 8-1 DDW PCB model top layer
Table 8-1 Dimension A for DDW package
Cu area (cm2)Dimension A (mm)
219.79
426.07
8

34.63

1646.54

32

63.25