Layout is a critical portion of good power supply
design. See Section 9.6.2 for a PCB layout example.
Users are recommended to include a large topside
area filled with ground. This top layer ground
area can be connected to the internal ground
layers using vias at the input bypass capacitor,
the output filter capacitor, and directly under
the TPS7H410x device to provide a thermal path
from the exposed thermal pad to ground. The
topside ground area together with the internal
ground plane must provide adequate heat
dissipating area.
Users are recommended that the thermal pad under
the TPS7H410x is tied to GND on internal ground
layers utilizing vias. The thermal pad does not
need to directly connect to ground on the top
layer to provide noise isolation between the
thermal pad ground and the topside PGND, which can
be noisy.
There are several signal paths that conduct fast
changing currents or voltages that can interact
with stray inductance or parasitic capacitance to
generate noise or degrade the power supply's
performance. To help eliminate these problems, the
PVIN pin can be bypassed to ground with a low ESR
ceramic bypass capacitor with an X7R
dielectric.
Take care minimize the loop area formed by the
bypass capacitor connections, the PVIN pins, and
the ground connections.
The VIN pin must also be bypassed to ground using
a low ESR ceramic capacitor with an X7R
dielectric. Make sure to connect this capacitor to
the quieter analog ground trace (if utilized)
rather than the power ground trace of the PVIN
bypass capacitor.
Since the SW connection is the switching node,
the output inductor can be located close to the SW
pins and the PCB conductor area minimized to
prevent excessive capacitive coupling.
The output filter capacitor ground can use the
same power ground as the PVIN input bypass
capacitor. Try to minimize this conductor length
while maintaining adequate width.
Keep the feedback trace away
from inductor EMI and other noise sources. Run the
feedback trace as far from the inductor, switch
(SW) node, and noisy power traces as possible.
Avoid routing this trace directly under the output
inductor if possible. If not possible, make sure
that the trace is routed on another layer with a
ground layer separating the trace and
inductor.
Keep the resistive divider
used to generate the VSNSx voltage as close to the
device pin as possible to reduce noise
pickup.
The RT and COMP pins are sensitive to noise, so
components around these pins can be located as
close as possible to the IC and routed with
minimal trace lengths.
Make all of the power (high
current) traces as short, direct, and thick as
possible.
Users can possibly obtain acceptable performance
with alternate PCB layouts.