SLVSHA4 June   2024 DRV8421

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings Comm
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 PWM Motor Drivers
      2. 7.3.2 Truth Tables
      3. 7.3.3 Parallel Operation
      4. 7.3.4 Protection Circuits
        1. 7.3.4.1 OCP
        2. 7.3.4.2 TSD
        3. 7.3.4.3 UVLO
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Bulk Capacitance Sizing
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Community Resources
    2. 9.2 Trademarks
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.3.2 Truth Tables

DRV8421A: 4-wire input version shows the logic for the inputs IN1, IN2, IN3, and IN4. DRV8421B: 2-wire input version shows the logic for the inputs IN1 and IN2.

Table 7-1 DRV8421A: 4-wire input version
Inputs Outputs Function
IN1 IN2 IN3 IN4 OUT1 OUT2 OUT3 OUT4
0 0 0 0 Off Off Off Off Standby (Hi-Z)
0 0 - Off Off - Channel 1 Standby (Hi-Z)
1 0 1 0 Forward
0 1 0 1 Reverse
1 1 0 0 Brake
- 0 0 - Off Off Channel 2 Standby (Hi-Z)
1 0 1 0 Forward
0 1 0 1 Reverse
1 1 0 0 Brake
DRV8421 Full-Step Mode Figure 7-4 Full-Step Mode
DRV8421 Half-Step Mode Figure 7-5 Half-Step Mode
Table 7-2 DRV8421B: 2-wire input version
Inputs Outputs Function
EN IN1 IN2 OUT1 OUT2 OUT3 OUT4
L X X Off Off Off Off Standby/Low Power Sleep Mode
H L - H L - Channel 1 Forward
H L H Reverse
- L - H L Channel 2 Forward
H L H Reverse
DRV8421 Full-Step Mode Figure 7-6 Full-Step Mode