SLVSHD4A October   2024  – March 2025 DRV8376

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements
    7. 6.7 SPI Slave Mode Timings
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Output Stage
      2. 7.3.2  Control Modes
        1. 7.3.2.1 6x PWM Mode (PWM_MODE = 00b or 01b or MODE_SR Pin Tied to AGND or in Hi-Z)
        2. 7.3.2.2 3x PWM Mode (PWM_MODE = 10b or 11b or MODE_SR Pin is Connected to GVDD or to GVDD with RMODE)
      3. 7.3.3  Device Interface Modes
        1. 7.3.3.1 Serial Peripheral Interface (SPI)
        2. 7.3.3.2 Hardware Interface
      4. 7.3.4  AVDD and GVDD Linear Voltage Regulator
      5. 7.3.5  Charge Pump
      6. 7.3.6  Slew Rate Control
      7. 7.3.7  Cross Conduction (Dead Time)
      8. 7.3.8  Propagation Delay
      9. 7.3.9  Pin Diagrams
        1. 7.3.9.1 Logic Level Input Pin (Internal Pulldown)
        2. 7.3.9.2 Logic Level Input Pin (Internal Pullup)
        3. 7.3.9.3 Open Drain Pin
        4. 7.3.9.4 Push Pull Pin
        5. 7.3.9.5 Four Level Input Pin
      10. 7.3.10 Current Sense Amplifiers
        1. 7.3.10.1 Current Sense Amplifier Operation
      11. 7.3.11 Active Demagnetization
        1. 7.3.11.1 Automatic Synchronous Rectification Mode (ASR Mode)
          1. 7.3.11.1.1 Automatic Synchronous Rectification in Commutation
          2. 7.3.11.1.2 Automatic Synchronous Rectification in PWM Mode
        2. 7.3.11.2 Automatic Asynchronous Rectification Mode (AAR Mode)
      12. 7.3.12 Cycle-by-Cycle Current Limit
        1. 7.3.12.1 Cycle by Cycle Current Limit with 100% Duty Cycle Input
      13. 7.3.13 Protections
        1. 7.3.13.1 VM Supply Undervoltage Lockout (RESET)
        2. 7.3.13.2 AVDD Undervoltage Protection (AVDD_UV)
        3. 7.3.13.3 GVDD Undervoltage Lockout (GVDD_UV)
        4. 7.3.13.4 VCP Charge Pump Undervoltage Lockout (CPUV)
        5. 7.3.13.5 Overvoltage Protections (OV)
        6. 7.3.13.6 Overcurrent Protection (OCP)
          1. 7.3.13.6.1 OCP Latched Shutdown (OCP_MODE = 00b)
          2. 7.3.13.6.2 OCP Automatic Retry (OCP_MODE = 01b)
          3. 7.3.13.6.3 OCP Report Only (OCP_MODE = 10b)
          4. 7.3.13.6.4 OCP Disabled (OCP_MODE = 11b)
        7. 7.3.13.7 Thermal Warning (OTW)
        8. 7.3.13.8 Thermal Shutdown (OTS)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Functional Modes
        1. 7.4.1.1 Sleep Mode
        2. 7.4.1.2 Operating Mode
        3. 7.4.1.3 Fault Reset (CLR_FLT or nSLEEP Reset Pulse)
      2. 7.4.2 DRVOFF Functionality
    5. 7.5 SPI Communication
      1. 7.5.1 Programming
        1. 7.5.1.1 SPI Format
  9. 8 Register Map
    1. 8.1 STATUS Registers
    2. 8.2 CONTROL Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Three-Phase Brushless-DC Motor Control
        1. 9.2.1.1 Detailed Design Procedure
          1. 9.2.1.1.1 Motor Voltage
          2. 9.2.1.1.2 Using Active Demagnetization
          3. 9.2.1.1.3 Current Limit Implementation
          4. 9.2.1.1.4 Current Sensing and Output Filtering
          5. 9.2.1.1.5 Power Dissipation and Junction Temperature Losses
        2. 9.2.1.2 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Bulk Capacitance
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
      3. 9.4.3 Thermal Considerations
        1. 9.4.3.1 Power Dissipation
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

8.1 STATUS Registers

Table 8-1 lists the memory-mapped registers for the STATUS registers. All register offset addresses not listed in Table 8-1 should be considered as reserved locations and the register contents should not be modified.

Table 8-1 STATUS Registers
Offset Acronym Register Name Section
0h Device Status Register Device Status Register Section 8.1.1
2h Device Raw Status Register Device Raw Status Register Section 8.1.2
4h Over Temperature Status Register Over Temperature Status Register Section 8.1.3
5h Supply Status Register Supply Status Register Section 8.1.4
6h Driver Status Register Driver Status Register Section 8.1.5
7h System Interface Status Register System Interface Status Register Section 8.1.6

Complex bit access types are encoded to fit into small table cells. Table 8-2 shows the codes that are used for access types in this section.

Table 8-2 STATUS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R
-0		 Read
Returns 0s
Reset or Default Value
-n Value after reset or the default value

8.1.1 Device Status Register (Offset = 0h) [Reset = 0280h]

Device Status Register is shown in Table 8-3.

Return to the Summary Table.

Table 8-3 Device Status Register Field Descriptions
Bit Field Type Reset Description
15 PARITY R 0h Parity Bit if SPI_PEN is set to '1' otherwise reserved
14-11 RESERVED R-0 0h Reserved
10 RESERVED R 0h Reserved
9 DNRDY_STS R 1h Device Not Ready Status. Will be cleared automatically after completion of Power Up.
  • 0h = Device is Ready
  • 1h = Device is NOT Ready
8 SYSFLT R 0h OTP Read fault occurred. Status remains latched until cleared by write to FLT_CLR or reset pulse on nSLEEP
  • 0h = No OTP read fault is detected
  • 1h = OTP read fault detected
7 RESET R 1h Device Reset status. Status remains latched until cleared by write to FLT_CLR or reset pulse on nSLEEP
  • 0h = Cleared Value
  • 1h = Device has undergone power on reset
6 SPIFLT R 0h SPI Fault status. Status remains latched until cleared by write to FLT_CLR or reset pulse on nSLEEP
  • 0h = No SPI fault is detected
  • 1h = SPI fault is detected
5 OCP R 0h Overcurrent Status. Status remains latched until cleared by write to FLT_CLR or reset pulse on nSLEEP
  • 0h = No overcurrent condition is detected
  • 1h = Overcurrent condition is detected
4 RESERVED R-0 0h Reserved
3 OVP R 0h Over Voltage Status. Status remains latched until cleared by write to FLT_CLR or reset pulse on nSLEEP
  • 0h = No over voltage condition is detected
  • 1h = Over voltage condition is detected
2 UVP R 0h Supply Undervoltage Status. Status remains latched until cleared by write to FLT_CLR or reset pulse on nSLEEP
  • 0h = No undervoltage voltage condition is detected on CP
  • 1h = Undervoltage voltage condition is detected on CP
1 OTF R 0h Overtemperature Fault Status. Status remains latched until cleared by write to FLT_CLR or reset pulse on nSLEEP
  • 0h = No overtemperature warning / shutdown is detected
  • 1h = Overtemperature warning / shutdown is detected
0 FAULT R 0h Device Fault status. Status remains latched until cleared by write to FLT_CLR or reset pulse on nSLEEP
  • 0h = No fault condition is detected
  • 1h = Fault condition is detected

8.1.2 Device Raw Status Register (Offset = 2h) [Reset = 0280h]

Device Raw Status Register is shown in Table 8-4.

Return to the Summary Table.

Table 8-4 Device Raw Status Register Field Descriptions
Bit Field Type Reset Description
15 PARITY R 0h Parity Bit if SPI_PEN is set to '1' otherwise reserved
14-13 RESERVED R-0 0h Reserved
12 DRVOFF_RSTS R 0h Status of DRV_OFF pin
  • 0h = DRV_OFF is not active
  • 1h = DRV_OFF is active
11 OTW_RSTS R 0h OT Warning Raw Status
  • 0h = OTW not active
  • 1h = OTW is active
10 RESERVED R 0h Reserved
9 DNRDY_RSTS R 1h Device Not Ready Status
  • 0h = Device is Ready
  • 1h = Device is NOT Ready
8 SYSFLT_RSTS R 0h OTP Read fault occurred. Status remains latched until cleared by write to FLT_CLR
  • 0h = No OTP read fault is detected
  • 1h = OTP read fault detected
7 RESET R 1h Device power on status. Status remains latched until cleared by write to FLT_CLR or reset pulse on nSLEEP
  • 0h = Cleared by FW after read
  • 1h = Device has undergone power on reset
6 SPIFLT_RSTS R 0h SPI Fault status. Status remains latched until cleared by write to FLT_CLR or reset pulse on nSLEEP
  • 0h = No SPI fault is detected
  • 1h = SPI fault is detected
5 OCP_RSTS R 0h Overcurrent Fault Raw Status. Status remains latched until completion of Auto Retry or write to FLT_CLR or reset pulse on nSLEEP.
  • 0h = Overcurrent condition is not active
  • 1h = Overcurrent condition is active
4 RESERVED R-0 0h Reserved
3 OVP_RSTS R 0h Over Voltage Raw Fault Status.
  • 0h = Over Voltage condition is not active.
  • 1h = Over Voltage condition is active.
2 UVP_RSTS R 0h CP Undervoltage Raw Fault Status.
  • 0h = Chare Pump Under voltage condition is not active.
  • 1h = Chare Pump Under voltage condition is active.
1 OTF_RSTS R 0h Overtemperature Shutdown Raw Fault Status.
  • 0h = Overtemperature shutdown is not active.
  • 1h = Overtemperature shutdown is active.
0 RESERVED R-0 0h Reserved

8.1.3 Over Temperature Status Register (Offset = 4h) [Reset = 0000h]

Over Temperature Status Register is shown in Table 8-5.

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Table 8-5 Over Temperature Status Register Field Descriptions
Bit Field Type Reset Description
15 PARITY R 0h Parity Bit if SPI_PEN is set to '1' otherwise reserved
14-2 RESERVED R-0 0h Reserved
1 OTW R 0h Overtemperature Warning Fault status. Can be cleared by write to FLT_CLR or reset pulse on nSLEEP
  • 0h = No overtemperature warning is detected
  • 1h = Overtemperature warning is detected
0 OTSD R 0h Overtemperature Shutdown Fault status. Can be cleared by write to FLT_CLR or reset pulse on nSLEEP
  • 0h = No overtemperature shutdown is detected
  • 1h = Overtemperature shutdown is detected

8.1.4 Supply Status Register (Offset = 5h) [Reset = 0000h]

Supply Status Register is shown in Table 8-6.

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Table 8-6 Supply Status Register Field Descriptions
Bit Field Type Reset Description
15 PARITY R 0h Parity Bit if SPI_PEN is set to '1' otherwise reserved
14-7 RESERVED R-0 0h Reserved
6 VM_OV R 0h Vm Over Voltage Fault Status
  • 0h = No Vm over voltage is detected
  • 1h = Vm over voltage is detected
5 RESERVED R-0 0h Reserved
4 CP_UV R 0h Charge Pump Undervoltage fault status
  • 0h = No charge pump undervoltage is detected
  • 1h = Charge pump undervoltage is detected
3-0 RESERVED R-0 0h Reserved

8.1.5 Driver Status Register (Offset = 6h) [Reset = 0000h]

Driver Status Register is shown in Table 8-7.

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Table 8-7 Driver Status Register Field Descriptions
Bit Field Type Reset Description
15 PARITY R 0h Parity Bit if SPI_PEN is set to '1' otherwise reserved
14-7 RESERVED R-0 0h Reserved
6 OCPC_HS R 0h Overcurrent Status on High-side switch of OUTC
  • 0h = No overcurrent detected on high-side MOSFET of OUTC
  • 1h = Overcurrent detected on high-side MOSFET of OUTC
5 OCPB_HS R 0h Overcurrent Status on High-side switch of OUTB
  • 0h = No overcurrent detected on high-side MOSFET of OUTB
  • 1h = Overcurrent detected on high-side MOSFET of OUTB
4 OCPA_HS R 0h Overcurrent Status on High-side switch of OUTA
  • 0h = No overcurrent detected on high-side MOSFET of OUTA
  • 1h = Overcurrent detected on high-side MOSFET of OUTA
3 RESERVED R-0 0h Reserved
2 OCPC_LS R 0h Overcurrent Status on Low-side switch of OUTC
  • 0h = No overcurrent detected on low-side MOSFET of OUTC
  • 1h = Overcurrent detected on low-side MOSFET of OUTC
1 OCPB_LS R 0h Overcurrent Status on Low-side switch of OUTB
  • 0h = No overcurrent detected on low-side MOSFET of OUTB
  • 1h = Overcurrent detected on low-side MOSFET of OUTB
0 OCPA_LS R 0h Overcurrent Status on Low-side switch of OUTA
  • 0h = No overcurrent detected on low-side MOSFET of OUTA
  • 1h = Overcurrent detected on low-side MOSFET of OUTA

8.1.6 System Interface Status Register (Offset = 7h) [Reset = 0000h]

System Interface Status Register is shown in Table 8-8.

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Table 8-8 System Interface Status Register Field Descriptions
Bit Field Type Reset Description
15 PARITY R 0h Parity Bit if SPI_PEN is set to '1' otherwise reserved
14-5 RESERVED R-0 0h Reserved
4 OTPLD_ERR R 0h OTP CRC error during load
  • 0h = No OTP read error is detected
  • 1h = OTP read error is detected
3 RESERVED R-0 0h Reserved
2 SPI_PARITY R 0h SPI Parity Error
  • 0h = No SPI Parity Error is detected
  • 1h = SPI Parity Error is detected
1 RESERVED R-0 0h Reserved
0 FRM_ERR R 0h SPI Frame Error
  • 0h = No SPI Frame Error is detected
  • 1h = SPI Frame Error is detected