SLVSHD4 Data sheet

SLVSHD4A October 2024 – March 2025 DRV8376

PRODUCTION DATA

8.2 CONTROL Registers

Table 8-9 lists the memory-mapped registers for the CONTROL registers. All register offset addresses not listed in Table 8-9 are considered as reserved locations and the register contents are not to be modified.

Table 8-9 CONTROL Registers

Offset	Acronym	Register Name	Section
10h	Fault Mode Register	Fault Mode Register	Section 8.2.1
13h	Drviver Fault Control Register	Drviver Fault Control Register	Section 8.2.2
17h	Fault Clear Register	Fault Clear Register	Section 8.2.3
20h	PWM Control Register 1	PWM Control Register 1	Section 8.2.4
22h	Predriver control Register	Predriver control Register	Section 8.2.5
23h	CSA Control Register	CSA Control Register	Section 8.2.6
3Fh	System Control Register	System Control Register	Section 8.2.7

Complex bit access types are encoded to fit into small table cells. Table 8-10 shows the codes that are used for access types in this section.

Table 8-10 CONTROL Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
R-0	R -0	Read Returns 0s
Write Type
W	W	Write
W1C	W 1C	Write 1 to clear
Reset or Default Value
-n		Value after reset or the default value

8.2.1 Fault Mode Register (Offset = 10h) [Reset = 2811h]

Fault Mode Register is shown in Table 8-11.

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Table 8-11 Fault Mode Register Field Descriptions

Bit	Field	Type	Reset	Description
15	PARITY	R	0h	Parity Bit if SPI_PEN is set to '1' otherwise reserved
14	RESERVED	R-0	0h	Reserved
13	ILIMFLT_MODE	R/W	1h	ILIMIT Fault mode 0h = ILIMIT reporting on nFAULT pin is disabled 1h = ILIMIT reporting on nFAULT pin is enabled
12-11	RESERVED	R/W	0h	Reserved
10	RESERVED	R-0	0h	Reserved
9	OVP_MODE	R/W	0h	Over Voltage Protection Fault mode 0h = Over Voltage protection is disabled 1h = Over Voltage protection is enabled
8	RESERVED	R-0	0h	Reserved
7	SPIFLT_MODE	R/W	0h	SPI Fault mode 0h = SPI fault reporting on nFAULT pin is disabled 1h = SPI fault reporting on nFAULT pin is enabled
6	RESERVED	R-0	0h	Reserved
5-4	OCP_MODE	R/W	1h	Overcurrent Protection Fault mode 0h = Over Current causes a latched fault 1h = Over Current causes an automatic retrying fault 2h = Over Current is report only but no action is taken 3h = Over Current is not reported and no action is taken
3-1	RESERVED	R-0	0h	Reserved
0	OTW_MODE	R/W	1h	Overtemperature Warning Fault mode 0h = Over temperature reporting on nFAULT is disabled 1h = Over temperature reporting on nFAULT is enabled

8.2.2 Drviver Fault Control Register (Offset = 13h) [Reset = 1010h]

Drviver Fault Control Register is shown in Table 8-12.

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Table 8-12 Drviver Fault Control Register Field Descriptions

Bit	Field	Type	Reset	Description
15	PARITY	R	0h	Parity Bit if SPI_PEN is set to '1' otherwise reserved
14	RESERVED	R-0	0h	Reserved
13-12	RESERVED	R/W	0h	Reserved
11	RESERVED	R-0	0h	Reserved
10	RESERVED	R/W	0h	Reserved
9	RESERVED	R-0	0h	Reserved
8	OVP_SEL	R/W	0h	Overvoltage level setting 0h = VM overvoltage level is 65V 1h = VM overvoltage level is 35V
7-6	RESERVED	R-0	0h	Reserved
5-4	OCP_DEG	R/W	1h	OCP Deglitch time 0h = OCP Deglitch time is 0.6 µs 1h = OCP Deglitch time is 1.25 µs 2h = OCP Deglitch time is 1.6 µs 3h = OCP Deglitch time is 2 µs
3	RESERVED	R-0	0h	Reserved
2	OCP_TRETRY	R/W	0h	OCP Retry Time 0h = 5ms 1h = 500ms
1	RESERVED	R-0	0h	Reserved
0	OCP_LVL	R/W	0h	OCP Level 0h = 4.5A 1h = 2.5A

8.2.3 Fault Clear Register (Offset = 17h) [Reset = 0000h]

Fault Clear Register is shown in Table 8-13.

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Table 8-13 Fault Clear Register Field Descriptions

Bit	Field	Type	Reset	Description
15	PARITY	R	0h	Parity Bit if SPI_PEN is set to '1' otherwise reserved
14-1	RESERVED	R-0	0h	Reserved
0	FLT_CLR	R-0/W1C	0h	Clear latched faults 0h = No clear fault command is issued 1h = To clear the latched fault bits. This bit automatically resets after being written.

8.2.4 PWM Control Register 1 (Offset = 20h) [Reset = 0020h]

PWM Control Register 1 is shown in Table 8-14.

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Table 8-14 PWM Control Register 1 Field Descriptions

Bit	Field	Type	Reset	Description
15	PARITY	R	0h	Parity Bit if SPI_PEN is set to '1' otherwise reserved
14-12	RESERVED	R/W	0h	Reserved
11	RESERVED	R/W	0h	Reserved
10	RESERVED	R/W	0h	Reserved
9-8	RESERVED	R/W	0h	Reserved
7-6	PWM_100_FREQ_SEL	R/W	0h	Frequency of PWM at 100% Duty cycle 0h = 20KHz 1h = 40KHz 2h = 10KHz 3h = None
5	ILIM_MODE	R/W	1h	Current limit recirculation settings 0h = Current recirculation through FETs (Brake mode) 1h = Current recirculation through diodes (coast mode)
4	RESERVED	R/W	0h	Reserved
3	EN_AAR	R/W	0h	Enable AAR where LS FET gets turned off when current goes negative. 0h = Active Demagnetization AAR is Disabled 1h = Active Demagnetization AAR is Enabled
2	EN_ASR	R/W	0h	Actie Demag Enable 0h = Active Demagnetization is Disabled 1h = Active Demagnetization is Enabled
1-0	PWM_MODE	R/W	0h	PWM mode selection 0h = 6x mode 1h = 6x mode 2h = 3x mode 3h = 3x mode

8.2.5 Predriver control Register (Offset = 22h) [Reset = 0080h]

Predriver control Register is shown in Table 8-15.

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Table 8-15 Predriver control Register Field Descriptions

Bit	Field	Type	Reset	Description
15	PARITY	R	0h	Parity Bit if SPI_PEN is set to '1' otherwise reserved
14-11	RESERVED	R-0	0h	Reserved
10-8	ILIM_BLANK_SEL	R/W	0h	Current Limit Blanking Time Selection 0h = 5.5us for slew rate of 50 and 1.8us for all other slew rates. 1h = 6.0us for slew rate of 50 and 2.3us for all other slew rates. 2h = 6.5us for slew rate of 50 and 2.8us for all other slew rates. 3h = 7.5us for slew rate of 50 and 3.8us for all other slew rates.
7-4	ADMAG_TMARGIN	R/W	8h	Wait time before determining HiZ. N4100ns
3	AD_COMP_TH_HS	R/W	0h	Active demag high side comparator threshold 0h = active demag comparator threshold is 100mA 1h = active demag comparator threshold is 150mA
2	AD_COMP_TH_LS	R/W	0h	Active demag low side comparator threshold 0h = active demag comparator threshold is 100mA 1h = active demag comparator threshold is 150mA
1-0	SLEW_RATE	R/W	0h	Slew rate settings 0h = Slew rate is 1100 V/µs 1h = Slew rate is 500 V/µs 2h = Slew rate is 250 V/µs 3h = Slew rate is 50 V/µs

8.2.6 CSA Control Register (Offset = 23h) [Reset = 0000h]

CSA Control Register is shown in Table 8-16.

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Table 8-16 CSA Control Register Field Descriptions

Bit	Field	Type	Reset	Description
15	PARITY	R	0h	Parity Bit if SPI_PEN is set to '1' otherwise reserved
14-2	RESERVED	R-0	0h	Reserved
1-0	CSA_GAIN	R/W	0h	CSA Gain settings 0h = CSA gain is 0.4 V/A 1h = CSA gain is 1.0 V/A 2h = CSA gain is 2.5 V/A 3h = CSA gain is 5.0 V/A

8.2.7 System Control Register (Offset = 3Fh) [Reset = 0008h]

System Control Register is shown in Table 8-17.

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Table 8-17 System Control Register Field Descriptions

Bit	Field	Type	Reset	Description
15	PARITY	R	0h	Parity Bit if SPI_PEN is set to '1' otherwise reserved
14-12	WRITE_KEY	R-0/W	0h	0x5 Write Key Specific to this register.
11	SDO_VSEL	R/W	0h	SDO Output Voltage Select 0h = AVDD 1h = GVDD
10	SDO_ODEN	R/W	0h	SDO in Open Drain Mode 0h = SDO in Push Pull Mode 1h = SDO in Open Drain Mode
9-8	RESERVED	R-0	0h	Reserved
7	REG_LOCK	R/W	0h	Register Lock Bit 0h = Registers Unlocked 1h = Registers Locked
6	SPI_PEN	R/W	0h	Parity Enable for SPI 0h = Parity Disabled 1h = Parity Enabled
5-4	RESERVED	R/W	0h	Reserved
3	RESERVED	R/W	0h	Reserved
2-0	RESERVED	R-0	0h	Reserved