SLVSHF4A November   2024  – October 2025 LP5899

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Thermal Information
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Internal Oscillator and Clocks
        1. 7.3.1.1 System Clock
        2. 7.3.1.2 Continuous Clock Serial Interface (CCSI) Clock
      2. 7.3.2 Continuous Clock Serial Interface (CCSI)
        1. 7.3.2.1 Command Format
        2. 7.3.2.2 Command Recognition and Synchronization
        3. 7.3.2.3 CCSI Command Queue
        4. 7.3.2.4 CCSI Start Bit and Check Bits Insertion and Removal
      3. 7.3.3 FIFO
        1. 7.3.3.1 FIFO level and Data Ready (DRDY) Interrupt
        2. 7.3.3.2 FIFO Clearance
      4. 7.3.4 Diagnostics
        1. 7.3.4.1  Undervoltage Lockout
        2. 7.3.4.2  Oscillator Fault Diagnostics
        3. 7.3.4.3  SPI Communications Loss
        4. 7.3.4.4  SPI Communications Error
          1. 7.3.4.4.1 Reset Timer
          2. 7.3.4.4.2 Chip Select (CS) Reset
          3. 7.3.4.4.3 CRC Error
          4. 7.3.4.4.4 Register write failure
        5. 7.3.4.5  CCSI Communications Loss
          1. 7.3.4.5.1 SIN Stuck-at Diagnostics
        6. 7.3.4.6  CCSI Communications Error
          1. 7.3.4.6.1 CHECK Bit Error
          2. 7.3.4.6.2 Data Integrity Diagnostics
          3. 7.3.4.6.3 CCSI Command Queue Overflow
        7. 7.3.4.7  FIFO Diagnostics
          1. 7.3.4.7.1 TXFIFO Overflow
          2. 7.3.4.7.2 TXFIFO Underflow
          3. 7.3.4.7.3 TXFIFO Single Error Detection (SED)
          4. 7.3.4.7.4 RXFIFO Overflow
          5. 7.3.4.7.5 RXFIFO Underflow
          6. 7.3.4.7.6 RXFIFO Single Error Detection (SED)
        8. 7.3.4.8  OTP CRC Error
        9. 7.3.4.9  Fault Masking
        10. 7.3.4.10 Diagnostics Table
    4. 7.4 Device Functional Modes
      1. 7.4.1 Unpowered
      2. 7.4.2 Initialization State
      3. 7.4.3 Normal State
      4. 7.4.4 Failsafe State
    5. 7.5 Programming
      1. 7.5.1 SPI Data Validity
      2. 7.5.2 Chip Select (CS) and SPI Reset Control
      3. 7.5.3 SPI Command Format
      4. 7.5.4 SPI Command Detail
  9. 8 Device Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Programming Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information
    2. 12.2 Mechanical Data

8 Device Registers

DEVICE Registers Summary Table lists the memory-mapped registers for the Device registers. All register offset addresses not listed in DEVICE Registers Summary Table are considered as reserved locations and the register contents are not modified.

Table 8-1 DEVICE Registers Summary Table
Address Acronym Description Section
0x0 DEVID Device Identification Section 8.1
0x1 SPICTRL Control for SPI Section 8.2
0x2 CCSICTRL Control for Continuous Clock Serial Interface (CCSI) Section 8.3
0x3 TXFFLVL Transmission FIFO level control Section 8.4
0x4 RXFFLVL Receive FIFO level control Section 8.5
0x5 DEVCTRL Control register for Device Section 8.6
0x6 DIAGMASK Diagnostic masking Section 8.7
0x7 STATUS Global device status Section 8.8
0x8 IFST Detail Interface status Section 8.9
0x9 TXFFST Detail Transmit FIFO status Section 8.10
0xA RXFFST Detail Receive FIFO status Section 8.11

Complex bit access types are encoded to fit into small table cells. Table 8-2 shows the codes that are used for access types in this section.

Table 8-2 Device Access Type Codes
Access Type Code Description
Read Type
R R Read
Write Type
W W Write
W1C W
1C		 Write
1 to clear
Reset or Default Value
-n Value after reset or the default value

8.1 DEVID Register (Address = 0x0) [Reset = 0xED99]

DEVID is shown in Figure 8-1 and described in Table 8-3.

Return to the DEVICE Registers Summary Table.

Figure 8-1 DEVID Register
15 14 13 12 11 10 9 8
DEVID
R-0xED99
7 6 5 4 3 2 1 0
DEVID
R-0xED99
Table 8-3 DEVID Register Field Descriptions
Bit Field Type Reset Description
15-0 DEVID R 0xED99 Device Identification

8.2 SPICTRL Register (Address = 0x1) [Reset = 0x00A0]

SPICTRL is shown in Figure 8-2 and described in Table 8-4.

Return to the DEVICE Registers Summary Table.

Figure 8-2 SPICTRL Register
15 14 13 12 11 10 9 8
RESERVED SPI_WDT_CFG RESERVED
R/W-0x0 R/W-0x0 R/W-0x0
7 6 5 4 3 2 1 0
SPI_RST_TIMEOUT_CFG RESERVED SPI_CRC_ALG SPI_SDO_DIS SPI_ACK_DIS
R/W-0xA R/W-0x0 R/W-0x0 R/W-0x0 R/W-0x0
Table 8-4 SPICTRL Register Field Descriptions
Bit Field Type Reset Description
15-14 RESERVED R/W 0x0 Reserved
13-12 SPI_WDT_CFG R/W 0x0 Watchdog on SPI to into FAILSAFE state
0x0 = 40ms
0x1 = 20ms
0x2 = 10ms
0x3 = Disabled
11-8 RESERVED R/W 0x0 Reserved
7-4 SPI_RST_TIMEOUT_CFG R/W 0xA Watchdog on SCLK to reset SPI after timeout
0x0 = Disabled
0x1 = 500us
0x2 = 1ms
0x3 = 2ms
0x4 = 3ms
0x5 = 4ms
0x6 = 5ms
0x7 = 10ms
0x8 = 15ms
0x9 = 20ms
0xA = 30ms
0xB = 40ms
0xC = 50ms
0xD = 85ms
0xE = 100ms
0xF = 200ms
3 RESERVED R/W 0x0 Reserved
2 SPI_CRC_ALG R/W 0x0 CRC algorithm used for SPI communication
0x0 = CCITT-FALSE is used
0x1 = CRC-16/XMODEM is used
1 SPI_SDO_DIS R/W 0x0 Disable bit for SPI SDO
0x0 = SDO is driven when CS is low
0x1 = SDO is always High Impedance
0 SPI_ACK_DIS R/W 0x0 Disable bit for SPI auto-reply of STATUS register
0x0 = Auto-reply is enabled
0x1 = Auto-reply is disabled

8.3 CCSICTRL Register (Address = 0x2) [Reset = 0x0000]

CCSICTRL is shown in Figure 8-3 and described in Table 8-5.

Return to the DEVICE Registers Summary Table.

Figure 8-3 CCSICTRL Register
15 14 13 12 11 10 9 8
RESERVED CCSI_SS_CLKO
R/W-0x0 R/W-0x0
7 6 5 4 3 2 1 0
RESERVED CCSI_DATA_RATE
R/W-0x0 R/W-0x0
Table 8-5 CCSICTRL Register Field Descriptions
Bit Field Type Reset Description
15-10 RESERVED R/W 0x0 Reserved
9-8 CCSI_SS_CLKO R/W 0x0 Spread spectrum setting for CLK_O pin
0x0 = disabled
0x1 = 2%
0x2 = 4%
0x3 = 8%
7-4 RESERVED R/W 0x0 Reserved
3-0 CCSI_DATA_RATE R/W 0x0 Data rate for CCSI
0x0 = 1Mbit/s
0x1 = 1.25Mbit/s
0x2 = 1.43Mbit/s
0x3 = 1.67Mbit/s
0x4 = 2Mbit/s
0x5 = 2.22Mbit/s
0x6 = 2.5Mbit/s
0x7 = 2.86Mbit/s
0x8 = 3.33Mbit/s
0x9 = 4Mbit/s
0xA = 5Mbit/s
0xB = 6.67Mbit/s
0xC = 8Mbit/s
0xD = 10Mbit/s
0xE = 13.33Mbit/s
0xF = 20Mbit/s

8.4 TXFFLVL Register (Address = 0x3) [Reset = 0x01FF]

TXFFLVL is shown in Figure 8-4 and described in Table 8-6.

Return to the DEVICE Registers Summary Table.

Figure 8-4 TXFFLVL Register
15 14 13 12 11 10 9 8
TXFFCLR RESERVED TXFFLVL
R/W1C-0x0 R/W-0x0 R/W-0x1FF
7 6 5 4 3 2 1 0
TXFFLVL
R/W-0x1FF
Table 8-6 TXFFLVL Register Field Descriptions
Bit Field Type Reset Description
15 TXFFCLR R/W1C 0x0 Clear all data on Transmit FIFO
14-9 RESERVED R/W 0x0 Reserved
8-0 TXFFLVL R/W 0x1FF TX FIFO level for start of transmission on CCSI in words with 0x0 meaning 1 word

8.5 RXFFLVL Register (Address = 0x4) [Reset = 0x00FF]

RXFFLVL is shown in Figure 8-5 and described in Table 8-7.

Return to the DEVICE Registers Summary Table.

Figure 8-5 RXFFLVL Register
15 14 13 12 11 10 9 8
RXFFCLR RESERVED
R/W1C-0x0 R/W-0x0
7 6 5 4 3 2 1 0
RXFFLVL
R/W-0xFF
Table 8-7 RXFFLVL Register Field Descriptions
Bit Field Type Reset Description
15 RXFFCLR R/W1C 0x0 Clear all data on Receive FIFO
14-8 RESERVED R/W 0x0 Reserved
7-0 RXFFLVL R/W 0xFF RX FIFO level to pull down the DRDY pin when number of words is exceeded with 0x0 meaning 1 word

8.6 DEVCTRL Register (Address = 0x5) [Reset = 0x0000]

DEVCTRL is shown in Figure 8-6 and described in Table 8-8.

Return to the DEVICE Registers Summary Table.

Figure 8-6 DEVCTRL Register
15 14 13 12 11 10 9 8
RESERVED
R/W-0x0
7 6 5 4 3 2 1 0
RESERVED FORCE_FS RESERVED EXIT_FS
R/W-0x0 R/W1C-0x0 R/W-0x0 R/W1C-0x0
Table 8-8 DEVCTRL Register Field Descriptions
Bit Field Type Reset Description
15-3 RESERVED R/W 0x0 Reserved
2 FORCE_FS R/W1C 0x0 Switch the device from NORMAL state to FAILSAFE state
0x0 = Keep current state
0x1 = Bring device to FAILSAFE state
1 RESERVED R/W 0x0 Reserved
0 EXIT_FS R/W1C 0x0 Bring device out of FAILSAFE mode to NORMAL mode

8.7 DIAGMASK Register (Address = 0x6) [Reset = 0x0000]

DIAGMASK is shown in Figure 8-7 and described in Table 8-9.

Return to the DEVICE Registers Summary Table.

Figure 8-7 DIAGMASK Register
15 14 13 12 11 10 9 8
RESERVED MASK_CCSI_CHECK
_BIT		 RESERVED MASK_CCSI_CRC MASK_CCSI_SIN
R/W-0x0 R/W-0x0 R/W-0x0 R/W-0x0 R/W-0x0
7 6 5 4 3 2 1 0
RESERVED MASK_SPI_CRC
R/W-0x0 R/W-0x0
Table 8-9 DIAGMASK Register Field Descriptions
Bit Field Type Reset Description
15-12 RESERVED R/W 0x0 Reserved
11 MASK_CCSI_CHECK_BIT R/W 0x0 Mask CCSI check bit fault to set FLAG_ERR and pull down FAULT pin
0x0 = Fault reporting is enabled
0x1 = Fault reporting is disabled
10 RESERVED R/W 0x0 Reserved
9 MASK_CCSI_CRC R/W 0x0 Mask CCSI CRC fault to set FLAG_ERR and pull down FAULT pin
0x0 = Fault reporting is enabled
0x1 = Fault reporting is disabled
8 MASK_CCSI_SIN R/W 0x0 Mask CCSI SIN stuck-at fault to set FLAG_ERR and pull down FAULT pin
0x0 = Fault reporting is enabled
0x1 = Fault reporting is disabled
7-1 RESERVED R/W 0x0 Reserved
0 MASK_SPI_CRC R/W 0x0 Mask SPI CRC fault to set FLAG_ERR and pull down FAULT pin
0x0 = Fault reporting is enabled
0x1 = Fault reporting is disabled

8.8 STATUS Register (Address = 0x7) [Reset = 0x0403]

STATUS is shown in Figure 8-8 and described in Table 8-10.

Return to the DEVICE Registers Summary Table.

Figure 8-8 STATUS Register
15 14 13 12 11 10 9 8
CLR_FLAG FLAG_CCSI RESERVED FLAG_TXFF FLAG_RXFF DRDYST FLAG_SRST FLAG_SPI
R/W1C-0x0 R-0x0 R-0x0 R-0x0 R-0x0 R-0x1 R-0x0 R-0x0
7 6 5 4 3 2 1 0
FLAG_SPI_REG
_WRITE		 FLAG_SPI_CRC DEV_STATE FLAG_OTP_CRC FLAG_OSC FLAG_POR FLAG_ERR
R-0x0 R-0x0 R-0x0 R-0x0 R-0x0 R-0x1 R-0x1
Table 8-10 STATUS Register Field Descriptions
Bit Field Type Reset Description
15 CLR_FLAG R/W1C 0x0 Write to clear all flags.
0x0 = Do not clear flags
0x1 = Clear all flags
14 FLAG_CCSI R 0x0 CCSI error flag.
0x0 = No device error has been detected
0x1 = Device error has been detected. Check IFST for more details.
13 RESERVED R 0x0 Reserved
12 FLAG_TXFF R 0x0 Transmit FIFO error detection.
0x0 = No Transmit FIFO error has been detected
0x1 = Transmit FIFO error has been detected. Check TXFFST for more details.
11 FLAG_RXFF R 0x0 Receive FIFO error detection.
0x0 = No Receive FIFO error has been detected
0x1 = Receive FIFO error has been detected. Check RXFFST for more details.
10 DRDYST R 0x1 Status of DRDY pin.
0x0 = DRDY pin is logic low
0x1 = DRDY pin is logic high
9 FLAG_SRST R 0x0 Unsuccessful SOFTRESET. Softreset cannot be executed while CCSI is transmitting.
0x0 = No SOFTRESET error has been detected
0x1 = SOFTRESET error has been detected
8 FLAG_SPI R 0x0 SPI error flag.
0x0 = No device error has been detected
0x1 = Device error has been detected. Check IFST for more details.
7 FLAG_SPI_REG_WRITE R 0x0 Unsuccessful SPI register write command. CCSICTRL cannot be written while CCSI is transmitting and/or receiving.
0x0 = No SPI register write error has been detected
0x1 = SPI register write error has been detected
6 FLAG_SPI_CRC R 0x0 SPI communication CRC error has been detected.
0x0 = No CRC error has been detected
0x1 = CRC error has been detected
5-4 DEV_STATE R 0x0 Device state.
0x0 = Device is in NORMAL state
0x1 = Device is in INIT state
0x2 = Device is in INIT state
0x3 = Device is in FAILSAFE state
3 FLAG_OTP_CRC R 0x0 OTP CRC error detection.
0x0 = No OTP CRC error has been detected
0x1 = OTP CRC error has been detected
2 FLAG_OSC R 0x0 Oscillator out of range detection.
0x0 = No oscillator error has been detected
0x1 = Oscillator error has been detected
1 FLAG_POR R 0x1 Power-On-Reset flag
0x0 = No POR is triggered
0x1 = Device has triggered POR
0 FLAG_ERR R 0x1 Global error flag. This is inverted status of FAULT pin.
0x0 = No error was detected
0x1 = One or more errors have been detected

8.9 IFST Register (Address = 0x8) [Reset = 0x0000]

IFST is shown in Figure 8-9 and described in Table 8-11.

Return to the DEVICE Registers Summary Table.

Figure 8-9 IFST Register
15 14 13 12 11 10 9 8
RESERVED FLAG_SPI_CS FLAG_SPI_TIMEOUT
R-0x0 R-0x0 R-0x0
7 6 5 4 3 2 1 0
RESERVED FLAG_CCSI_CMD
_QUEUE_OVF		 FLAG_CCSI_CHECK
_BIT		 RESERVED FLAG_CCSI_CRC FLAG_CCSI_SIN
R-0x0 R-0x0 R-0x0 R-0x0 R-0x0 R-0x0
Table 8-11 IFST Register Field Descriptions
Bit Field Type Reset Description
15-10 RESERVED R 0x0 Reserved
9 FLAG_SPI_CS R 0x0 SPI Chip Select pin was pulled high in the middle of reception of command.
0x0 = No CS error has been detected
0x1 = CS error has been detected
8 FLAG_SPI_TIMEOUT R 0x0 SPI timeout error has been detected. This is only be set when SPI_RST_TIMEOUT_CFG is enabled.
0x0 = No SPI timeout has been detected
0x1 = SPI timeout has been detected
7-5 RESERVED R 0x0 Reserved
4 FLAG_CCSI_CMD_QUEUE_OVF R 0x0 CCSI command queue overflow error has been detected.
0x0 = No overflow error has been detected
0x1 = Overflow error has been detected
3 FLAG_CCSI_CHECK_BIT R 0x0 CCSI check bit error has been detected for CCSI received data.
0x0 = No check bit error has been detected
0x1 = Check bit error has been detected
2 RESERVED R 0x0 Reserved
1 FLAG_CCSI_CRC R 0x0 CRC error has been detected for CCSI data.
0x0 = No CRC error has been detected
0x1 = CRC error has been detected
0 FLAG_CCSI_SIN R 0x0 Missing toggling on SIN.
0x0 = No missing toggling on SIN error has been detected
0x1 = Missing toggling on SIN error has been detected

8.10 TXFFST Register (Address = 0x9) [Reset = 0x0000]

TXFFST is shown in Figure 8-10 and described in Table 8-12.

Return to the DEVICE Registers Summary Table.

Figure 8-10 TXFFST Register
15 14 13 12 11 10 9 8
FLAG_TXFFOVF FLAG_TXFFUVF FLAG_TXFFSED RESERVED TXFFST
R-0x0 R-0x0 R-0x0 R-0x0 R-0x0
7 6 5 4 3 2 1 0
TXFFST
R-0x0
Table 8-12 TXFFST Register Field Descriptions
Bit Field Type Reset Description
15 FLAG_TXFFOVF R 0x0 Overflow error on Transmit FIFO
14 FLAG_TXFFUVF R 0x0 Underflow error on Transmit FIFO
13 FLAG_TXFFSED R 0x0 Single Error Detection on Transmit FIFO
12-9 RESERVED R 0x0 Reserved
8-0 TXFFST R 0x0 TX FIFO Status
0x0 = Transmit FIFO is empty.
0x1 = Transmit FIFO has 1 word.
0x2 = Transmit FIFO has 2 words.
...
0x1FE = Transmit FIFO has 510 words.
0x1FF = Transmit FIFO has 511 or 512 words.

8.11 RXFFST Register (Address = 0xA) [Reset = 0x0000]

RXFFST is shown in Figure 8-11 and described in Table 8-13.

Return to the DEVICE Registers Summary Table.

Figure 8-11 RXFFST Register
15 14 13 12 11 10 9 8
FLAG_RXFFOVF FLAG_RXFFUVF FLAG_RXFFSED RESERVED
R-0x0 R-0x0 R-0x0 R-0x0
7 6 5 4 3 2 1 0
RXFFST
R-0x0
Table 8-13 RXFFST Register Field Descriptions
Bit Field Type Reset Description
15 FLAG_RXFFOVF R 0x0 Overflow error on Receive FIFO
14 FLAG_RXFFUVF R 0x0 Underflow error on Receive FIFO
13 FLAG_RXFFSED R 0x0 Single Error Detection on Receive FIFO
12-8 RESERVED R 0x0 Reserved
7-0 RXFFST R 0x0 RX FIFO Status
0x0 = Receive FIFO is empty.
0x1 = Receive FIFO has 1 word.
0x2 = Receive FIFO has 2 words.
...
0xFE = Receive FIFO has 254 words.
0xFF = Receive FIFO has 255 or 256 words.