SLVSHK0 December   2025 UCD91160

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Linearity Parameters
    7. 5.7 POR and BOR
    8. 5.8 Low Frequency Crystal/Clock
    9. 5.9 Flash Memory Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 TI Sequencer Studio Software
      2. 6.3.2 PMBUS Interface
      3. 6.3.3 PMBUS Security
    4. 6.4 Device Functional Modes
      1. 6.4.1 Black Box First Fault Logging
      2. 6.4.2 PMBus Address Selection
      3. 6.4.3 Brownout
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

7.2.1 Design Requirements

UCD91160 requires decoupling capacitors on the VDD, BPCAP, and VREF+ pins. The capacitance values for VDD, BPCAP, and VREF+ are specified in the Electrical Characteristics. Consider these capacitor design configurations as options.

  • If an application does not use the nRESET signal, the nRESET pin must be tied to VDD, either by direct connection to the VDD pin, or by an R-C circuit as shown in Figure 7-2. The R-C circuit in Figure 7-2 can be also used to delay reset at power up. If an application uses the nRESET external pin, the trace of the nRESET signal must be kept as short as possible. Be sure to place any components connected to the nRESET signal as close to the device as possible.
  • Holding the nRESET pin low for <1s triggers a BOOT Reset, and holding nRESET low for >1s triggers a POR/Power On Reset.
  • The analog monitoring pins are capable of monitoring voltage rails between 0V and 3.3V. The input of the MONx pin should not move outside of this range.
  • It is mandatory that the VDD power be stable and no device reset be fired during the device programming. Resets triggered while the device is programming can cause corruption.

  • TI recommends connecting a combination of a 10µF and a 0.1µF low-ESR ceramic decoupling capacitor across the VDD and VSS pins, as well as placing the capacitors as close as possible to the supply pins. The 10µF bulk decoupling capacitor is a recommended value for most applications, but this capacitance can be adjusted if needed based upon the PCB design and application requirements. For example, larger bulk capacitors can be used, but this can affect the supply rail ramp-up time.

  • A 0.47µF tank capacitor is required for the BPCAP pin and must be placed close to the device with minimum distance to the device ground. Do not connect other circuits to the BPCAP pin.
UCD91160 nRESET Pin With R-C NetworkFigure 7-2 nRESET Pin With R-C Network