SLVSHK0 December   2025 UCD91160

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Linearity Parameters
    7. 5.7 POR and BOR
    8. 5.8 Low Frequency Crystal/Clock
    9. 5.9 Flash Memory Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 TI Sequencer Studio Software
      2. 6.3.2 PMBUS Interface
      3. 6.3.3 PMBUS Security
    4. 6.4 Device Functional Modes
      1. 6.4.1 Black Box First Fault Logging
      2. 6.4.2 PMBus Address Selection
      3. 6.4.3 Brownout
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

4 Pin Configuration and Functions

UCD91160 UCD91160PM Package, 64-Pin LQFP (Top View)Figure 4-1 UCD91160PM Package, 64-Pin LQFP (Top View)
Table 4-1 Pin Functions

PIN

TYPE

Pin ID

DESCRIPTION

NAME

NO.

MONITORING INPUTS (MONx)

MON1

31

I

1

Analog or Digital Monitor (0V – 3.3V)

MON2

30

I

2

Analog or Digital Monitor (0V – 3.3V)

MON3

26

I

3

Analog or Digital Monitor (0V – 3.3V)

MON4

25

I

4

Analog or Digital Monitor (0V – 3.3V)

MON5

27

I

5

Analog or Digital Monitor (0V – 3.3V)

MON6

23

I

6

Analog or Digital Monitor (0V – 3.3V)

MON7

19

I

7

Analog or Digital Monitor (0V – 3.3V)

MON8

7

I

8

Analog or Digital Monitor (0V – 3.3V)

MON9

8

I

9

Analog Monitor (0V – 3.3V)(1)

MON10

9

I

10

Analog or Digital Monitor (0V – 3.3V)

MON11

10

I

11

Analog or Digital Monitor (0V – 3.3V)

MON12

11

I

12

Analog Monitor (0V – 3.3V)(1)

MON13

14

I

13

Analog or Digital Monitor (0V – 3.3V)

MON14

15

I

14

Analog or Digital Monitor (0V – 3.3V)

MON15

16

I

15

Analog or Digital Monitor (0V – 3.3V)

MON16

18

I

16

Analog Monitor (0V – 3.3V)(1)

Rail Enables (ENx)

EN1(GPIO)

49

I/O

33

Rail enable signal, digital output, or GPIO

EN2(GPIO)

48

I/O

34

Rail enable signal, digital output, or GPIO

EN3(GPIO)

51

I/O

35

Rail enable signal, digital output, or GPIO

EN4(GPIO)

53

I/O

36

Rail enable signal, digital output, or GPIO

EN5(GPIO)

47

I/O

37

Rail enable signal, digital output, or GPIO

EN6(GPIO)

46

I/O

38

Rail enable signal, digital output, or GPIO

EN7(GPIO)

45

I/O

39

Rail enable signal, digital output, or GPIO

EN8(GPIO)

60

I/O

40

Rail enable signal, digital output, or GPIO

EN9(GPIO)

1

I/O

41

Rail enable signal, digital output, or GPIO

EN10(GPIO)

2

I/O

42

Rail enable signal, digital output, or GPIO

EN11(GPIO)

28

I/O

43

Rail enable signal, digital output, or GPIO

EN12(GPIO)

29

I/O

44

Rail enable signal, digital output, or GPIO

EN13(GPIO)

37

I/O

45

Rail enable signal, digital output, or GPIO

EN14(GPIO)

42

I/O

46

Rail enable signal, digital output, or GPIO

EN15(GPIO)

61

I/O

47

Rail enable signal, digital output, or GPIO

EN16(GPIO)

64

I/O

48

Rail enable signal, digital output, or GPIO

Closed-Loop Margin Pins (MARx)

MAR1(GPIO)

50

I/O

65

Closed-loop margin PWM output, or GPIO

MAR2(GPIO)

55

I/O

66

Closed-loop margin PWM output, or GPIO

MAR3(GPIO)

52

I/O

67

Closed-loop margin PWM output, or GPIO

MAR4(GPIO)

54

I/O

68

Closed-loop margin PWM output, or GPIO

MAR5(GPIO)

56

I/O

69

Closed-loop margin PWM output, or GPIO

MAR6(GPIO)

57

I/O

70

Closed-loop margin PWM output, or GPIO

MAR7(GPIO)

58

I/O

71

Closed-loop margin PWM output, or GPIO

MAR8(GPIO)

59

I/O

72

Closed-loop margin PWM output, or GPIO

PMBus COMM INTERFACE

PMBUS_CLK

39

I/O

N/A

PMBus clock (must have pullup to 3.3V)

PMBUS_DATA

35

I/O

N/A

PMBus data (must have pullup to 3.3V)

PMBUS_ALERT

34

O

N/A

PMBus alert, active-low, open-drain output (must have pullup to 3.3V)

PMBUS_CNTRL

33

I

N/A

PMBus control (must have pullup to 3.3V)

PMBUS_ADDR020IN/APMBUS Address Select
PMBUS_ADDR121IN/APMBUS Address Select
PMBUS_ADDR222IN/APMBUS Address Select

Logical General Purpose Outputs (LGPOx)

LGPO1 (GPIO)3I/O81Boolean-Logical Output, or GPIO
LGPO2 (GPIO)4

I/O

82Boolean-Logical Output, or GPIO
LGPO3 (GPIO)5

I/O

83

Boolean-Logical Output, or GPIO
LGPO4 (GPIO)6

I/O

84

Boolean-Logical Output, or GPIO
LGPO5 (GPIO)62

I/O

85

Boolean-Logical Output, or GPIO
LGPO6 (GPIO)63

I/O

86

Boolean-Logical Output, or GPIO

LGPO7 (GPIO)

12

I/O

87

Boolean-Logical Output, or GPIO

LGPO8 (GPIO)

13

I/O

88

Boolean-Logical Output, or GPIO

INPUT POWER, GROUNDS, AND CLOCKING

LFXOUT

44

CLK

N/A

Low-frequency crystal out

LFXIN

43

CLK

N/A

Low-frequency crystal in

nRESET

38

I

N/A

Active-low device reset input. Recommend pulling up to VDD if not required by application. Hold low for at least 1.5μs to perform a boot reset, or 1s for a power-on-reset (POR)

SYNC_CLK

36

O

N/ASynchronization clock I/O (5kHz) for multiple chip cascading

VREF+

24

I

N/A(Optional) positive node of external reference voltage

VREF-

17

P

N/A(Optional) negative node of external reference voltage(1)

VDD

40

P

N/A

Input 3V to 3.6V supply. Refer to the Layout Guidelines section

VSS

41

P

N/A

Device ground

BPCAP

32

P

N/A

0.47µF bypass capacitor. Refer to the Layout Guidelines section

1.

Utilize MON9 only as an analog monitoring pin

1.

Utilize pin 11 - MON12 only as an analog monitoring pin

1.

Utilize pin 18 - MON16 only as an analog monitoring pin

1.

When the VREF- pin is not utilized, connect it to ground.