SLVSHK6 Data sheet

SLVSHK6A March 2025 – March 2026 TPS61381-Q1

PRODUCTION DATA

8.2.2.5.1 Small Signal Analysis

The TPS61381-Q1 uses the fixed frequency peak current mode control with an internal adaptive slope compensation to avoid subharmonic oscillation. With the inductor current information sensed, the small-signal model of the power stage reduces from a two-pole system, created by L and C_OUT, to a single-pole system, created by R_OUT and C_OUT. The single-pole system is easily used with the loop compensation. The image below shows the equivalent small signal elements of a boost converter.

TPS61381-Q1 TPS61381-Q1 Control Equivalent
Circuitry Model

Figure 8-3 TPS61381-Q1 Control Equivalent Circuitry Model

The small signal of power stage can be given by:

Equation 13.

K_{P S} (s) = \frac{R_{o u t} (1 - D)}{2 R_{s e n s e}} \times \frac{(1 + \frac{s}{2 π \times f_{z E S R}}) (1 - \frac{s}{2 π \times f_{z R H P}})}{(1 + \frac{s}{2 π \times f_{p P S}})}

where

D is the duty cycle
R_out is the output load resistance
R_sense is the equivalent internal current sense resistor, which is typically 6mΩ

The single pole of the power stage can be given by:

Equation 14.

f_{p P S} = \frac{2}{2 π \times C_{o u t} \times R_{o u t}}

where

C_out is the output capacitance. For a boost converter having multiple identical output capacitors in parallel, simply combine the capacitors with the equivalent capacitance

The zero created by the ESR of the output capacitor can be given by:

Equation 15.

f_{z E S R} = \frac{1}{2 π \times C_{o u t} \times R_{E S R}}

where

R_ESR is the equivalent resistance in series of the output capacitor

The right-hand plane zero can be given by:

Equation 16.

f_{z R H P} = \frac{R_{o u t} (1 - D)^{2}}{2 π \times L}

where

D is the duty cycle
R_out is the output load resistor
L is the inductance

Equation 17 shows the equation for feedback resistor network and the compensation network.

Equation 17.

H_{C O M P} (s) = G_{c o m p} \times R_{E A} \times \frac{R_{u p} + R_{d o w n}}{R_{d o w n}} \times \frac{(1 + \frac{s}{2 π \times f_{z C O M P}})}{(s 1 + \frac{s}{2 π \times f_{p C O M P 1}}) (1 + \frac{s}{2 π \times f_{p C O M P 2}})}

where

G_COMP is the gain of the error amplifier, typically G_EA = 24uS
R_EA is the output impedance of the error amplifier, typically R_EA = 5 MΩ
ƒ_pCOMP1, ƒ_pCOMP2 is the pole's frequency of the compensation
f_zCOMP is the zero’s frequency of the compensation network

ƒ_pCOMP1 can be given by:

Equation 18.

f_{p C O M P 1} = \frac{1}{2 π \times R_{E A} \times C_{C O M P}}

where

C_COMP is the compensation capacitor

ƒ_pCOMP2 can be given by:

Equation 19.

f_{p C O M P 2} = \frac{1}{2 π \times R_{C O M P} \times C_{H F}}

where

C_HF is the high frequency bypass capacitor on COMP pin
R_COMP is the resistor of the compensation network

ƒ_zCOMP can be given by:

Equation 20.

f_{z C O M P} = \frac{1}{2 π \times R_{C O M P} \times C_{C O M P}}

where

C_COMP is the zero capacitor compensation
R_COMP is the resistor of the compensation network