SLVSHQ2A December   2024  – April 2025 DRV8351-SEP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings Comm
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Diagrams
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Three BLDC Gate Drivers
        1. 7.3.1.1 Gate Driver Timings
          1. 7.3.1.1.1 Propagation Delay
          2. 7.3.1.1.2 Dead Time and Cross-Conduction Prevention
        2. 7.3.1.2 Mode (Inverting and non inverting INLx)
      2. 7.3.2 Pin Diagrams
      3. 7.3.3 Gate Driver Protective Circuits
        1. 7.3.3.1 VBSTx Undervoltage Lockout (BSTUV)
        2. 7.3.3.2 GVDD Undervoltage Lockout (GVDDUV)
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Bootstrap Capacitor and GVDD Capacitor Selection
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.3.2 Pin Diagrams

Figure 7-5 shows the input structure for the logic level pins INHx, INLx. INHx and non-inverted INLx has passive pull down, so when inputs are floating the output the gate driver is pulled low. Figure 7-6 shows the input structure for the inverted INLx pins. The inverted INLx has passive pull up, so when inputs are floating the output of the low-side gate driver is pulled low.

DRV8351-SEP INHx and non-inverted INLx Logic-Level Input Pin StructureFigure 7-5 INHx and non-inverted INLx Logic-Level Input Pin Structure
DRV8351-SEP Inverted INLx Logic-Level Input Pin StructureFigure 7-6 Inverted INLx Logic-Level Input Pin Structure