SLVSHR6A July   2025  – November 2025 TPS1686

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Logic Interface
    7. 6.7 Timing Requirements
    8. 6.8 Switching Characteristics
    9. 6.9 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Undervoltage Protection
      2. 7.3.2  Insertion Delay
      3. 7.3.3  Overvoltage Protection
      4. 7.3.4  Inrush Current, Overcurrent, and Short-Circuit Protection
        1. 7.3.4.1 Slew Rate (dVdt) and Inrush Current Control
          1. 7.3.4.1.1 Start-Up Time Out
        2. 7.3.4.2 Steady-State Overcurrent Protection (circuit-breaker)
        3. 7.3.4.3 Active Current Limiting During Start-Up
        4. 7.3.4.4 Short-Circuit Protection
      5. 7.3.5  Analog Load Current Monitor (IMON)
      6. 7.3.6  Switch Enable Pin (SWEN)
      7. 7.3.7  Analog Junction Temperature Monitor (TEMP)
      8. 7.3.8  Overtemperature Protection
      9. 7.3.9  Fault Response and Indication (FLT)
      10. 7.3.10 Power Good Indication (PG)
      11. 7.3.11 Output Discharge
      12. 7.3.12 FET Health Monitoring
      13. 7.3.13 Single Point Failure Mitigation
        1. 7.3.13.1 IMON Pin Single Point Failure
        2. 7.3.13.2 IREF Pin Single Point Failure
        3. 7.3.13.3 ITIMER Pin Single Point Failure
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Single Device, Standalone Operation
    2. 8.2 Typical Application: 54V Fan Load Protection in Datacenter Servers
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Application Performance Plots
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Transient Protection
      2. 8.3.2 Output Short-Circuit Measurements
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Third-Party Products Disclaimer
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.3.9 Fault Response and Indication (FLT)

Table 7-4 summarizes the device response to various fault conditions.

Table 7-4 Fault Summary
EVENT OR CONDITION DEVICE RESPONSE FAULT LATCHED INTERNALLY FLT PIN STATUS DELAY

Steady-state

None

N/A

H

Inrush

None

N/A

H

Overtemperature

Shutdown

Y

L

Undervoltage (EN/UVLO)

Shutdown

N

H

Undervoltage (VDD UVP)

Shutdown

N

H

Undervoltage (VIN UVP)

Shutdown

N

H

Overvoltage (VIN OVP)

Shutdown

N

H

Transient overcurrent

None

N

H

Persistent overcurrent (steady-state)

Circuit-Breaker

Y

L

tITIMER

Persistent overcurrent (start-up)

Current Limit

N

L

Short-circuit

Fast-trip

Y

L

tFT

IMON pin open (steady-state)

Shutdown

Y

L

IMON pin short (steady-state)

Shutdown (If IOUT > IOC_BKP)

Y

L

50μs

IREF pin open (start-up)

Shutdown (If IOUT > IOC_BKP)

Y?

L?

IREF pin open (steady-state)

Shutdown (if IOUT > IOC_BKP)

Y

L

tITIMER

IREF pin short (steady-state)

Shutdown

Y

L

IREF pin short (start-up)

Shutdown

Y

L

ITIMER pin forced to high voltage

Shutdown (if IOUT > IOCP or IOUT > IOC_BKP)

Y

L

tSPFAIL_TMR

Start-up timeout

Shutdown

Y

L

tSU_TMR

FET health fault (G-S)

Shutdown

Y

L

10μs

FET health fault (G-D)

Shutdown

Y

L

FET health fault (D-S)

Shutdown

N

L

tSU_TMR

External fault (SWEN pulled low externally while device is not in UV or OV)

Shutdown

Y

L

FLT is an open-drain pin and must be pulled up to an external supply.

For faults that are latched internally, power cycling the part or pulling the EN/UVLO pin voltage below VSD(F) clears the fault and the pin is de-asserted. This action also clears the tRST timer (auto-retry variants only). Pulling the EN/UVLO just below the UVLO threshold has no impact on the device in this condition. This is true for both latch-off and auto-retry variants.