SLVSHS7A October   2024  – June 2025 TPSI31P1-Q1

PRODUCTION DATA  

1.   1
2. 1 Features
3. 2 Applications
4. 3 Description
5. 4 Pin Configuration and Functions
6. 5 Specifications
   1. 5.1  Absolute Maximum Ratings
   2. 5.2  ESD Ratings
   3. 5.3  Recommended Operating Conditions
   4. 5.4  Thermal Information
   5. 5.5  Power Ratings
   6. 5.6  Insulation Specifications
   7. 5.7  Safety-Related Certifications
   8. 5.8  Safety Limiting Values
   9. 5.9  Electrical Characteristics
   10. 5.10 Switching Characteristics
   11. 5.11 Insulation Characteristic Curves
7. 6 Detailed Description
   1. 6.1 Overview
   2. 6.2 Functional Block Diagram
   3. 6.3 Feature Description
      1. 6.3.1 Transmission of the Enable State
      2. 6.3.2 Power Transmission
      3. 6.3.3 Gate Driver
      4. 6.3.4 Chip Enable (CE)
      5. 6.3.5 Comparators
      6. 6.3.6 VDDP, VDDH, and VDDM Under-voltage Lockout (UVLO)
      7. 6.3.7 Keep-off Circuitry
      8. 6.3.8 Thermal Shutdown
   4. 6.4 Device Functional Modes
8. 7 Application and Implementation
   1. 7.1 Application Information
   2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
         1. 7.2.2.1 CDIV1, CDIV2 Capacitance
      3. 7.2.3 Application Curves
      4. 7.2.4 Insulation Lifetime
   3. 7.3 Power Supply Recommendations
   4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
9. 8 Device and Documentation Support
   1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
   2. 8.2 Receiving Notification of Documentation Updates
   3. 8.3 Support Resources
   4. 8.4 Trademarks
   5. 8.5 Electrostatic Discharge Caution
   6. 8.6 Glossary
10. 9 Revision History
11. 10Mechanical, Packaging, and Orderable Information