SLVSHS7A October   2024  – June 2025 TPSI31P1-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety-Related Certifications
    8. 5.8  Safety Limiting Values
    9. 5.9  Electrical Characteristics
    10. 5.10 Switching Characteristics
    11. 5.11 Insulation Characteristic Curves
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Transmission of the Enable State
      2. 6.3.2 Power Transmission
      3. 6.3.3 Gate Driver
      4. 6.3.4 Chip Enable (CE)
      5. 6.3.5 Comparators
      6. 6.3.6 VDDP, VDDH, and VDDM Under-voltage Lockout (UVLO)
      7. 6.3.7 Keep-off Circuitry
      8. 6.3.8 Thermal Shutdown
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 CDIV1, CDIV2 Capacitance
      3. 7.2.3 Application Curves
      4. 7.2.4 Insulation Lifetime
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

4 Pin Configuration and Functions

Figure 4-1 TPSI31P1-Q1 DVX Package, 16-Pin SSOP(Top View)
PIN I/O TYPE(1) DESCRIPTION
NO. NAME
1 EN I — Active high pre-charge enable. Internal 500kΩ pull-down to VSSP.
2 CE I — Active high chip enable. When asserted low, device is disabled. Tie to VDDP or EN when not used. Internal 500kΩ pull-down to VSSP.
4 VDDP — P Power supply for the primary side.
5 PGOOD O — Power good indicator. Open-drain output. When being used, requires external pull-up to VDDP. Float or tie to VSSP when not used.
11, 12 IS+ I — Resistor shunt positive. When voltage across shunt resistor exceeds internal reference voltage (1.23V), VDRV is asserted low and remains low until voltage across shunt resistor falls below internal reference (160mV). Internal 2.8MΩ pull-down to VSSS. Connect both IS+ pins together in the application.
13 VDDM — P Generated mid-supply, nominal 5V.
15 VDDH — P Generated high supply, nominal 17V.
16 VDRV O — Active high driver output.
6,7 NC NC — No connect. Connect both NC pins to VSSP.
3, 8 VSSP — GND Ground supply for the primary side. All VSSP pins must be connected to the primary side ground.
9, 10, 14 VSSS — GND Ground supply for the secondary side. All VSSS pins must be connected to the secondary side ground.
(1) P = power, GND = ground, NC = no connect