SLVSIC8 December   2025 TPSM852892

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  VCC Power Supply
      2. 6.3.2  EXTVCC Power Supply
      3. 6.3.3  Input Undervoltage Lockout
      4. 6.3.4  Enable and Programmable UVLO
      5. 6.3.5  Soft Start
      6. 6.3.6  Shutdown
      7. 6.3.7  Switching Frequency
      8. 6.3.8  Switching Frequency Dithering
      9. 6.3.9  Inductor Current Limit
      10. 6.3.10 Internal Charge Path
      11. 6.3.11 Output Voltage Setting
      12. 6.3.12 Output Current Monitoring and Cable Voltage Droop Compensation
      13. 6.3.13 Output Current Limit
      14. 6.3.14 Overvoltage Protection
      15. 6.3.15 Output Short Circuit Protection
      16. 6.3.16 Power Good
      17. 6.3.17 Constant Current Output Indication
      18. 6.3.18 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 PWM Mode
      2. 6.4.2 Power Save Mode
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Switching Frequency
        2. 7.2.2.2 Output Voltage Setting
        3. 7.2.2.3 Input Capacitor
        4. 7.2.2.4 Output Capacitor
        5. 7.2.2.5 Output Current Limit
        6. 7.2.2.6 Loop Stability
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Third-Party Products Disclaimer
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

4 Pin Configuration and Functions

Figure 4-1 TPSM852892 RYQ Package, 71-Pin VQFN-HR (Transparent Top View)
Table 4-1 Pin Functions
PIN I/O DESCRIPTION
NAME NO.
AGND 23 - Signal ground of the IC.
BOOT1 69 O Power supply for high-side MOSFET gate driver in buck side. A ceramic capacitor of 0.1µF is integrated between this pin and the SW1 pin. Leave this pin floating.
BOOT2 70 O Power supply for high-side MOSFET gate driver in boost side. A ceramic capacitor of 0.1µF is integrated between this pin and the SW2 pin. Leave this pin floating.
CC 47 O Constant current output indication open drain output. When output current limit is triggered, this pin outputs low level.
CDC 22 O Voltage output proportional to the sensed voltage between the ISP pin and the ISN pin. Use a resistor between this pin and AGND to increase the output voltage to compensate voltage droop across the cable caused by the cable resistance.
COMP 21 O Output of the internal error amplifier. Connect the loop compensation network between this pin and the AGND pin.
DITH/SYNC 48 I Dithering frequency setting and synchronous clock input. Use a capacitor between this pin and ground to set the dithering frequency. When this pin is short to ground or pulled above 1.2V, there is no dithering function. An external clock can be applied at this pin to synchronize the switching frequency.
EN/UVLO 44 I Enable logic input and programmable input voltage undervoltage lockout (UVLO) input. Logic high level enables the device. Logic low level disables the device and turns it into shutdown mode. After the voltage at the EN/UVLO pin is above the logic high voltage of 1.15V, this pin acts as programmable UVLO input with 1.23V internal reference.
EXTVCC 43 I Select the internal LDO or external 5V for VCC. When it is connected to logic high voltage or is left floating, select the internal LDO. When it is connected to logic low voltage, select the external 5V for VCC.
FB 20 I Connect to the center of a resistor divider to program the output voltage
FSW 49

I

 The switching frequency is programmed by a resistor between this pin and the AGND pin.
ISN 19 I Negative input of the current sense amplifier. An optional current sense resistor connected between the ISP pin and the ISN pin can limit the output current. If the sensed voltage reaches the current limit, a slow constant current control loop becomes active and starts to regulate the voltage between the ISP pin and the ISN pin. Connecting the ISP pin and the ISN pin together with the VOUT pin can disable the output current limit function. Do not leave floating.
ISP 18 I Positive input of the current sense amplifier. An optional current sense resistor connected between the ISP pin and the ISN pin can limit the output current. If the sensed voltage reaches the current limit, a slow constant current control loop becomes active and starts to regulate the voltage between the ISP pin and the ISN pin. Connecting the ISP pin and the ISN pin together with the VOUT pin can disable the output current limit function. Do not leave floating.
L1 40-41, 61, 67 PWR The terminal of the internal integrated inductor, connect this pin with SW1.
L2 26-27, 58, 64 PWR The terminal of the internal integrated inductor, connect this pin with SW2.
MODE 45 I Mode selection pin in light load condition. When it is connected to logic high voltage, the device works in forced PWM mode. When it is connected to logic low voltage, the device works in auto PFM mode. This pin can not be float in application.
NC 17, 25, 42, 50 - Not connected internally, connect NC with AGND.
PG 46 O Power good indication open drain output. When the output voltage is above 95% of the setting output voltage, this pin outputs high impedance. When the output voltage is below 90% of the setting output voltage, this pin outputs low level
PGND 6-9, 28-39, 55 PWR IC power ground.
SW1 62, 66, 68 PWR Buck side switching node pin. It is connected to the drain of the internal buck low-side power MOSFET and the source of internal buck high-side power MOSFET.
SW2 63, 65, 71 PWR Boost side switching node pin. It is connected to the drain of the internal boost low-side power MOSFET and the source of internal boost high-side power MOSFET.
VCC 24 O Internal regulator output. A ceramic capacitor of more than 4.7μF is required between this pin and the AGND pin.
VIN 1-5, 51-54, 60 PWR Buck-boost module input.
VOUT 10-16, 56-57, 59 PWR Buck-boost module output.