SLVSIH2 May   2026 TPS61129-Q1

ADVMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Synchronous Rectifier and True Shutdown
      2. 7.3.2 Device Enable
      3. 7.3.3 Down Mode Threshold
      4. 7.3.4 SYNC/MODE Configuration
      5. 7.3.5 Output Discharge
      6. 7.3.6 Soft Start and Short-Circuit Protection
      7. 7.3.7 Power-Good Indicator
      8. 7.3.8 Spread Spectrum Frequency Modulation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Undervoltage Lockout
    5. 7.5 Programming
      1. 7.5.1 Programming the Output Voltage
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Inductor Selection
        2. 8.2.2.2 Input Capacitor Selection
        3. 8.2.2.3 Output Capacitor Selection
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information

8.2.2.3 Output Capacitor Selection

The output capacitor is mainly selected to meet the requirements for output ripple and loop stability. The ripple voltage is related to capacitor capacitance and the equivalent series resistance (ESR). Assuming a ceramic capacitor with zero ESR, use Equation 5 to calculate the minimum capacitance needed for a given ripple voltage.

Equation 5. TPS61129-Q1

where

  • DMAX is the maximum switching duty cycle.
  • VRIPPLE is the peak-to-peak output ripple voltage.
  • IOUT is the maximum output current.
  • fSW is the switching frequency.

The ESR impact on the output ripple must be considered if tantalum or aluminum electrolytic capacitors are used. Use Equation 6 to calculate the output peak-to-peak ripple voltage caused by the ESR of the output capacitors.

Equation 6. TPS61129-Q1

Take care when evaluating the derating of a ceramic capacitor under DC bias voltage, aging, and AC signal. For example, the DC bias voltage can significantly reduce capacitance. A ceramic capacitor can lose more than 50% of the capacitance at the rated voltage. Therefore, always leave margin on the voltage rating to make sure there is adequate capacitance at the required output voltage. Increasing the output capacitor makes the output ripple voltage smaller in forced PWM mode.

TI recommends using the X5R or X7R ceramic output capacitor in the range of 10μF to 1000μF effective capacitance. The 22μF effective capcaitance is typically utilized in middle load conditions. The output capacitor affects the small signal control loop stability of the boost regulator. If the output capacitor is below the recommended range, the boost regulator can potentially become unstable.