SLVSIH2 May   2026 TPS61129-Q1

ADVMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Synchronous Rectifier and True Shutdown
      2. 7.3.2 Device Enable
      3. 7.3.3 Down Mode Threshold
      4. 7.3.4 SYNC/MODE Configuration
      5. 7.3.5 Output Discharge
      6. 7.3.6 Soft Start and Short-Circuit Protection
      7. 7.3.7 Power-Good Indicator
      8. 7.3.8 Spread Spectrum Frequency Modulation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Undervoltage Lockout
    5. 7.5 Programming
      1. 7.5.1 Programming the Output Voltage
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Inductor Selection
        2. 8.2.2.2 Input Capacitor Selection
        3. 8.2.2.3 Output Capacitor Selection
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information

7.3.6 Soft Start and Short-Circuit Protection

When the input voltage is above the UVLO threshold and the EN pin is pulled high, the TPS61129-Q1 is enabled. To limit the inrush current and power dissipation on the high-side FET, the peak switching current limit is gradually released from 500mA to the normal current limit of 3.5A (typical), based on the voltage at the VOUT pin and working mode. There are a total of three phases during start-up, as summarized in the Table 7-1.

Under abnormal operating conditions, such as when the VOUT pin is shorted to the GND, the device behaves exactly as described in PHASE I .

Table 7-1 Peak Switching Current Limit in Different Work Conditions, With VIN = 3.3V, VOUT = 5V
PHASE NUMBER VIN and VOUT CONDITIONS TYPICAL PEAK SWITCHING CURRENT LIMIT
I VOUT < 2.2V 0.5A
II (Down mode) 2.4V < VOUT < VIN + Vdown_mode(1) 1.5A
III (Boost mode) VIN + Vdown_mode < VOUT(1) 3.5A
(1) Vdown_mode = 235mV for down mode entering, Vdown_mode = 285mV for down mode existence.