SLVSIL9 July   2025 SN54SC1G125-SEP

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Balanced CMOS 3-State Outputs
      2. 7.3.2 Standard CMOS Inputs
      3. 7.3.3 Clamp Diode Structure
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
    3. 8.3 Design Requirements
      1. 8.3.1 Power Considerations
      2. 8.3.2 Input Considerations
      3. 8.3.3 Output Considerations
    4. 8.4 Detailed Design Procedure
    5. 8.5 Application Curves
    6. 8.6 Power Supply Recommendations
    7. 8.7 Layout
      1. 8.7.1 Layout Guidelines
      2. 8.7.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

6 Parameter Measurement Information

Phase relationships between waveforms were chosen arbitrarily for the examples listed in the following table. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1MHz, ZO = 50Ω, tt ≤ 2.5ns.

The outputs are measured individually with one input transition per measurement.

Table 6-1 3-State Outputs
TEST S1 S2
tPLH, tPHL OPEN OPEN
tPLZ, tPZL CLOSED OPEN
tPHZ, tPZH OPEN CLOSED

Table 6-2 3-State or Open-Drain Outputs
VCC Vt RL CL ΔV VLOAD
1.2V ± 0.1V VCC/2 2kΩ 15pF 0.1V 2×VCC
1.5V ± 0.12V VCC/2 2kΩ 15pF 0.1V 2×VCC
1.8V ± 0.15V VCC/2 1kΩ 15pF/30pF 0.15V 2×VCC
2.5V ± 0.2V VCC/2 500Ω 15pF/30pF 0.15V 2×VCC
3.3V ± 0.3V 1.5V 500Ω 15pF/50pF 0.3V 6V
5.0V ± 0.5V 1.5V 500Ω 15pF/50pF 0.3V 6V

SN54SC1G125-SEP Load Circuit for 3-State Outputs
(1) CL includes probe and test-fixture capacitance.
Figure 6-1 Load Circuit for 3-State Outputs
SN54SC1G125-SEP Voltage Waveforms Propagation Delays
(1) The greater between tPZL and tPZH is the same as ten.
(2) The greater between tPLZ and tPHZ is the same as tdis.
Figure 6-3 Voltage Waveforms Propagation Delays
SN54SC1G125-SEP Voltage Waveforms Propagation Delays
(1) The greater between tPLH and tPHL is the same as tpd.
Figure 6-2 Voltage Waveforms Propagation Delays
SN54SC1G125-SEP Voltage Waveforms, Input and Output Transition Times
(1) The greater between tr and tf is the same as tt.
Figure 6-4 Voltage Waveforms, Input and Output Transition Times