SLVSIL9
July 2025
SN54SC1G125-SEP
ADVANCE INFORMATION
1
1
Features
2
Applications
3
Description
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics
5.6
Switching Characteristics
5.7
Typical Characteristics
6
Parameter Measurement Information
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Balanced CMOS 3-State Outputs
7.3.2
Standard CMOS Inputs
7.3.3
Clamp Diode Structure
7.4
Device Functional Modes
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.3
Design Requirements
8.3.1
Power Considerations
8.3.2
Input Considerations
8.3.3
Output Considerations
8.4
Detailed Design Procedure
8.5
Application Curves
8.6
Power Supply Recommendations
8.7
Layout
8.7.1
Layout Guidelines
8.7.2
Layout Example
9
Device and Documentation Support
9.1
Documentation Support
9.1.1
Related Documentation
9.2
Receiving Notification of Documentation Updates
9.3
Support Resources
9.4
Trademarks
9.5
Electrostatic Discharge Caution
9.6
Glossary
10
Revision History
11
Mechanical, Packaging, and Orderable Information
1
Features
VID TBD-01XE
Radiation - Total Ionizing Dose (TID):
TID characterized up to 50 krad(Si)
TID performance assurance up to 30 krad(Si)
Radiation Lot Acceptance Testing (RLAT) for every wafer lot up to 30 krad(Si)
Radiation - Single-Event Effects (SEE):
Single Event Latch-Up (SEL) immune up to 50 MeV-cm
2
/mg at 125°C
Single Event Transient (SET) characterized up to LET = 50 MeV-cm
2
/mg
Wide operating range of 1.2V to 5.5V
5.5V tolerant input pins
Supports standard pinouts
Up to 150Mbps with 5V or 3.3V V
CC
Latch-up performance exceeds 100mA per JESD 78
Space enhanced plastic:
Supports Defense and Aerospace Applications
Controlled baseline
Au bondwire and NiPdAu lead finish
Meets NASA ASTM E595 outgassing specification
One fabrication, assembly, and test site
Extended product life cycle
Product traceability