SLVSIL9 July   2025 SN54SC1G125-SEP

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Balanced CMOS 3-State Outputs
      2. 7.3.2 Standard CMOS Inputs
      3. 7.3.3 Clamp Diode Structure
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
    3. 8.3 Design Requirements
      1. 8.3.1 Power Considerations
      2. 8.3.2 Input Considerations
      3. 8.3.3 Output Considerations
    4. 8.4 Detailed Design Procedure
    5. 8.5 Application Curves
    6. 8.6 Power Supply Recommendations
    7. 8.7 Layout
      1. 8.7.1 Layout Guidelines
      2. 8.7.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5.6 Switching Characteristics

over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted). See #i#Parameter Measurement Information
PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE VCC -55°C to 125°C UNIT
MIN TYP MAX
tpd A Y CL = 15 pF 1.2V ± 0.1V 27 41.5 ns
tpd A Y CL = 15 pF 1.5V ± 0.12V 8 9.1 ns
tpd A Y CL = 15 pF 1.8V ± 0.15V 6 6.9 ns
tpd A Y CL = 15 pF 2.5V ± 0.2V 3.9 4.6 ns
tpd A Y CL = 15 pF 3.3V ± 0.3V 2.8 3.7 ns
tpd A Y CL = 15 pF 5.0V ± 0.5V 2 3.4 ns
tpd A Y CL = 30 pF 1.8V ± 0.15V 2.8 6 9.3 ns
tpd A Y CL = 30 pF 2.5V ± 0.2V 1.2 4 5.8 ns
tpd A Y CL = 50 pF 3.3V ± 0.3V 1 3.4 4.9 ns
tpd A Y CL = 50 pF 5.0V ± 0.5V 1 2.6 4 ns
ten OE Y CL = 15 pF 1.2V ± 0.1V 30 44 ns
ten OE Y CL = 15 pF 1.5V ± 0.12V 8 9.5 ns
ten OE Y CL = 15 pF 1.8V ± 0.15V 6 7.4 ns
ten OE Y CL = 15 pF 2.5V ± 0.2V 3 4.3 ns
ten OE Y CL = 15 pF 3.3V ± 0.3V 2 3.2 ns
ten OE Y CL = 15 pF 5.0V ± 0.5V 1.5 2.2 ns
ten OE Y CL = 30 pF 1.8V ± 0.15V 3.1 7.3 10.4 ns
ten OE Y CL = 30 pF 2.5V ± 0.2V 1.5 4.1 6.9 ns
ten OE Y CL = 50 pF 3.3V ± 0.3V 1 3.3 5.8 ns
ten OE Y CL = 50 pF 5.0V ± 0.5V 1 2.6 5 ns
tdis OE Y CL = 15 pF 1.2V ± 0.1V 23 30 ns
tdis OE Y CL = 15 pF 1.5V ± 0.12V 8 10.8 ns
tdis OE Y CL = 15 pF 1.8V ± 0.15V 7 8.5 ns
tdis OE Y CL = 15 pF 2.5V ± 0.2V 4 5.1 ns
tdis OE Y CL = 15 pF 3.3V ± 0.3V 4 4.4 ns
tdis OE Y CL = 15 pF 5.0V ± 0.5V 2.5 3.4 ns
tdis OE Y CL = 30 pF 1.8V ± 0.15V 1.3 8 9.4 ns
tdis OE Y CL = 30 pF 2.5V ± 0.2V 1 4 5.5 ns
tdis OE Y CL = 50 pF 3.3V ± 0.3V 1 4 5 ns
tdis OE Y CL = 50 pF 5.0V ± 0.5V 1 3 4.2 ns
Cpd outputs enabled f = 10 MHz 1.8V 18 pf
Cpd outputs disabled f = 10 MHz 1.8V 2 pf
Cpd outputs enabled f = 10 MHz 2.5V 18 pf
Cpd outputs disabled f = 10 MHz 2.5V 2 pf
Cpd outputs enabled f = 10 MHz 3.3V 19 pf
Cpd outputs disabled f = 10 MHz 3.3V 2 pf
Cpd outputs enabled f = 10 MHz 5V 21 pf
Cpd outputs disabled f = 10 MHz 5V 4 pf