SLVSIN3 May   2025 ADS9117 , ADS9118 , ADS9119

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Thermal Information
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements
    7. 6.7  Switching Characteristics
    8. 6.8  Timing Diagrams
    9. 6.9  Typical Characteristics: All Devices
    10. 6.10 Typical Characteristics: ADS9119
    11. 6.11 Typical Characteristics: ADS9118
    12. 6.12 Typical Characteristics: ADS9117
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
      2. 7.3.2 Analog Input Bandwidth
      3. 7.3.3 ADC Transfer Function
      4. 7.3.4 Reference Voltage
      5. 7.3.5 Temperature Sensor
      6. 7.3.6 Data Averaging
      7. 7.3.7 Digital Down Converter
      8. 7.3.8 Data Interface
        1. 7.3.8.1 Data Frame Width
        2. 7.3.8.2 ADC Output Data Randomizer
        3. 7.3.8.3 Synchronizing Multiple ADCs
        4. 7.3.8.4 Test Patterns for Data Interface
          1. 7.3.8.4.1 Fixed Pattern
          2. 7.3.8.4.2 Alternating Test Pattern
          3. 7.3.8.4.3 Digital Ramp
      9. 7.3.9 ADC Sampling Clock Input
    4. 7.4 Device Functional Modes
      1. 7.4.1 Reset
      2. 7.4.2 Power-Down Options
      3. 7.4.3 Normal Operation
      4. 7.4.4 Initialization Sequence
    5. 7.5 Programming
      1. 7.5.1 Register Write
      2. 7.5.2 Register Read
      3. 7.5.3 Multiple Devices: Daisy-Chain Topology for SPI Configuration
        1. 7.5.3.1 Register Write With Daisy-Chain
        2. 7.5.3.2 Register Read With Daisy-Chain
  9. 8 Register Map
    1. 8.1 Register Bank 0
    2. 8.2 Register Bank 1
    3. 8.3 Register Bank 2
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Data Acquisition (DAQ) Circuit for a ≤20kHz Input Signal Bandwidth
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Data Acquisition (DAQ) Circuit for a ≤100kHz Input Signal Bandwidth
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Application Curves
      3. 9.2.3 Data Acquisition (DAQ) Circuit for a ≤1MHz Input Signal Bandwidth
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Mechanical Data

8.1 Register Bank 0

Figure 8-1 Register Bank 0 Map
ADD D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
00hRESERVEDSPI_MODESPI_RD_ENRESET
01hRESERVEDDAISY_CHAIN_LENRESERVED
03hRESERVEDREG_BANK_SEL
04hRESERVEDINIT_1
06hREG_00H_READBACK
Table 8-1 Register Section/Block Access Type Codes
Access TypeCodeDescription
RRRead
WWWrite
R/WR/WRead or write
Reset or Default Value
-nValue after reset or the default value

8.1.2 Register 00h (offset = 0h) [reset = 0h]

Figure 8-2 Register 00h
15141312111098
RESERVED
W-0h
76543210
RESERVEDSPI_MODESPI_RD_ENRESET
W-0hW-0hW-0hW-0h
Figure 8-3 Register 00h Field Descriptions
BitFieldTypeResetDescription
15-3RESERVEDW0hReserved. Do not change from the default reset value.
2SPI_MODEW0hSelect between legacy SPI mode and daisy-chain SPI mode for the configuration interface to enable register access.
0 : Daisy-chain SPI mode
1 : Legacy SPI mode
1SPI_RD_ENW0hEnable register read access in legacy SPI mode. This bit has no effect in daisy-chain SPI mode.
0 : Register read disabled
1 : Register read enabled
0RESETW0hADC reset control.
0 : Normal device operation
1 : Resets the ADC and all registers

8.1.3 Register 01h (offset = 1h) [reset = 0h]

Figure 8-4 Register 01h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDDAISY_CHAIN_LENRESERVED
R/W-0hR/W-0hR/W-0h
Figure 8-5 Register 01h Field Descriptions
BitFieldTypeResetDescription
15-7RESERVEDR/W0hReserved. Do not change from the default reset value.
6-2DAISY_CHAIN_LENR/W0hConfigure the number of ADCs connected in daisy-chain for the SPI configuration.
0 : 1 ADC
1 : 2 ADCs
31 : 32 ADCs
1-0RESERVEDR/W0hReserved. Do not change from the default reset value.

8.1.4 Register 03h (offset = 3h) [reset = 2h]

Figure 8-6 Register 03h
15141312111098
RESERVED
R/W-0h
76543210
REG_BANK_SEL
R/W-2h
Figure 8-7 Register 03h Field Descriptions
BitFieldTypeResetDescription
15-8RESERVEDR/W0hReserved. Do not change from the default reset value.
7-0REG_BANK_SELR/W2hRegister bank selection for read and write operations.
0 : Select register bank 0
2 : Select register bank 1
16 : Select register bank 2

8.1.5 Register 04h (offset = 4h) [reset = 0h]

Figure 8-8 Register 04h
15141312111098
RESERVED
R-0h
76543210
RESERVEDINIT_1
R/W-0h
Figure 8-9 Register 04h Field Descriptions
BitFieldTypeResetDescription
3-0INIT_1R/W0hINIT_1 field for device initialization. Write 1011b during the initialization sequence. Write 0000b for normal operation.

8.1.6 Register 06h (offset = 6h) [reset = 2h]

Figure 8-10 Register 06h
15141312111098
REG_00H_READBACK
R-0h
76543210
REG_00H_READBACK
R-5h
Figure 8-11 Register 06h Field Descriptions
BitFieldTypeResetDescription
15-0REG_00H_READBACKR2hThis register is a copy of the register address 0x00 for readback. The register address 0x00 is write-only. The default readback value is 2h because SPI_RD_EN in address 0x00 is set to 1 for register reads.