SLVSIN3 May   2025 ADS9117 , ADS9118 , ADS9119

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Thermal Information
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements
    7. 6.7  Switching Characteristics
    8. 6.8  Timing Diagrams
    9. 6.9  Typical Characteristics: All Devices
    10. 6.10 Typical Characteristics: ADS9119
    11. 6.11 Typical Characteristics: ADS9118
    12. 6.12 Typical Characteristics: ADS9117
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
      2. 7.3.2 Analog Input Bandwidth
      3. 7.3.3 ADC Transfer Function
      4. 7.3.4 Reference Voltage
      5. 7.3.5 Temperature Sensor
      6. 7.3.6 Data Averaging
      7. 7.3.7 Digital Down Converter
      8. 7.3.8 Data Interface
        1. 7.3.8.1 Data Frame Width
        2. 7.3.8.2 ADC Output Data Randomizer
        3. 7.3.8.3 Synchronizing Multiple ADCs
        4. 7.3.8.4 Test Patterns for Data Interface
          1. 7.3.8.4.1 Fixed Pattern
          2. 7.3.8.4.2 Alternating Test Pattern
          3. 7.3.8.4.3 Digital Ramp
      9. 7.3.9 ADC Sampling Clock Input
    4. 7.4 Device Functional Modes
      1. 7.4.1 Reset
      2. 7.4.2 Power-Down Options
      3. 7.4.3 Normal Operation
      4. 7.4.4 Initialization Sequence
    5. 7.5 Programming
      1. 7.5.1 Register Write
      2. 7.5.2 Register Read
      3. 7.5.3 Multiple Devices: Daisy-Chain Topology for SPI Configuration
        1. 7.5.3.1 Register Write With Daisy-Chain
        2. 7.5.3.2 Register Read With Daisy-Chain
  9. 8 Register Map
    1. 8.1 Register Bank 0
    2. 8.2 Register Bank 1
    3. 8.3 Register Bank 2
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Data Acquisition (DAQ) Circuit for a ≤20kHz Input Signal Bandwidth
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Data Acquisition (DAQ) Circuit for a ≤100kHz Input Signal Bandwidth
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Application Curves
      3. 9.2.3 Data Acquisition (DAQ) Circuit for a ≤1MHz Input Signal Bandwidth
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Mechanical Data

8.2 Register Bank 1

Figure 8-12 Register Bank 1 Map
ADD D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0Dh RESERVED DATA_FORMAT RESERVED LAT_INC GE_CAL_EN1 OSR_EN OSR RESERVED
10h RESERVED HI_FREQ
12h RESERVED XOR_EN DATA_LANES
13h RESERVED RAMP_INC TP_MODE TP_EN RESERVED
14h TP0
15h TP1 TP0
16h TP1
1Ch RESERVED USER_BITS_ADC_A
33h RESERVED GE_CAL_EN3 RESERVED GE_CAL_EN2 RESERVED
34h RESERVED LAT_EN RESERVED
90h RESERVED TS_LD RESERVED
91h RESERVED TEMPERATURE_SENSOR
C0h RESERVED CLK1 OSR_INIT1 OSR_CLK RESERVED PD_CH
C1h RESERVED PD_REF RESERVED DATA_RATE RESERVED CLK2
C4h RESERVED OSR_INIT2 RESERVED OSR_INIT3 PD_CHIP
C5h RESERVED HI_FREQ_EN RESERVED CLK3 RESERVED RD_CLK RESERVED CLK4 RESERVED
FBh RESERVED NCO_SYSREF XOR_MODE CLK5 MIXER_EN
FCh NCO_PHASE_COUNT[15:0]
FDh NCO_FREQUENCY[7:0] NCO_PHASE_COUNT[23:16]
FEh NCO_FREQUENCY[23:8]
Table 8-2 Register Section/Block Access Type Codes
Access Type Code Description
R R Read
W W Write
R/W R/W Read or write
Reset or Default Value
-n Value after reset or the default value

Register 0Dh (offset = Dh) [reset = 2002h]

Figure 8-13 Register 0Dh
15 14 13 12 11 10 9 8
RESERVED DATA_FORMAT RESERVED LAT_INC
R/W-0h R/W-1h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
GE_CAL_EN1 OSR_EN OSR RESERVED
R/W-0h R/W-0h R/W-0h R/W-2h
Figure 8-14 Register 0Dh Field Descriptions
Bit Field Type Reset Description
15-14 RESERVED R/W 0h Reserved. Do not change from the default reset value.
13 DATA_FORMAT R/W 1h Select data format for the ADC conversion result.
0 : Straight-binary format
1 : Two's-complement format
12-10 RESERVED R/W 0h Reserved. Do not change from the default reset value.
9-8 LAT_INC R/W 0h For the ADS9119, set this field to 11b for optimum INL performance.
7 GE_CAL_EN1 R/W 0h Global control for gain error calibration.
0 : Gain error calibration disabled
1 : Gain error calibration enabled
6 OSR_EN R/W 0h Control for data averaging depth.
0 : Data averaging disabled
1 : Data averaging enabled
5-2 OSR R/W 0h Control for enabling data averaging.
0 : 2 samples averaged
1 : 4 samples averaged
2 : 8 samples averaged
3 : 16 samples averaged
1-0 RESERVED R/W 2h Reserved. Do not change from the default reset value.

8.2.1 Register 10h (offset = 10h) [reset = 0h]

Figure 8-15 Register 10h
15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
RESERVED RESERVED
R/W-0h R/W-0h
Figure 8-16 Register 10h Field Descriptions
Bit Field Type Reset Description
15-1 RESERVED R/W 0h Reserved. Do not change from the default reset value.
0 HI_FREQ R/W 0h Analog input fast slew rate control
0: Normal slew rate.
1: Fast slew rate. Fast analog input control enabled. Recommended for input frequencies >2MHz. Also see the HI_FREQ_EN register bit.

8.2.2 Register 12h (offset = 12h) [reset = 2h]

Figure 8-17 Register 12h
15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
RESERVED XOR_EN DATA_LANES
R/W-0h R/W-0h R/W-2h
Figure 8-18 Register 12h Field Descriptions
Bit Field Type Reset Description
15-4 RESERVED R/W 0h Reserved. Do not change from the default reset value.
3 XOR_EN R/W 0h Enables XOR operation on ADC conversion result.
0 : XOR operation is disabled
1 : ADC conversion result is bit-wise XOR with the PRBS bit by default
2-0 DATA_LANES R/W 2h Selects the number of output data lanes and number of data bits per output lane.
0 : 20 bits per data output frame on DOUT.
2 : 24 bits per data output frame on DOUT.

8.2.3 Register 13h (offset = 13h) [reset = 0h]

Figure 8-19 Register 13h
15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
RAMP_INC TP_MODE TP_EN RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h
Figure 8-20 Register 13h Field Descriptions
Bit Field Type Reset Description
15-8 RESERVED R/W 0h Reserved. Do not change from the default reset value.
7-4 RAMP_INC R/W 0h Increment value for the ramp pattern output. The output ramp increments by N+1, where N is the value configured in this register.
3-2 TP_MODE R/W 0h Select digital test pattern for ADC.
0 : Fixed pattern from the TP0 register
1 : Fixed pattern from the TP0 register
2 : Digital ramp output
3 : Alternate fixed pattern output from the TP0 and TP1 registers
1 TP_EN R/W 0h Enable digital test pattern for data corresponding to ADC.
0 : Data output is the ADC conversion result
1 : Data output is the digital test pattern for ADC
0 RESERVED R/W 0h Reserved. Do not change from the default reset value.

8.2.4 Register 14h (offset = 14h) [reset = 0h]

Figure 8-21 Register 14h
15 14 13 12 11 10 9 8
TP0[15:0]
R/W-0h
7 6 5 4 3 2 1 0
TP0[15:0]
R/W-0h
Figure 8-22 Register 14h Field Descriptions
Bit Field Type Reset Description
15-0 TP0[15:0] R/W 0h Lower 16 bits of test pattern 0

8.2.5 Register 15h (offset = 15h) [reset = 0h]

Figure 8-23 Register 15h
15 14 13 12 11 10 9 8
TP1[7:0]
R/W-0h
7 6 5 4 3 2 1 0
TP0[23:16]
R/W-0h
Figure 8-24 Register 15h Field Descriptions
Bit Field Type Reset Description
15-8 TP1[7:0] R/W 0h Lower eight bits of test pattern 1
7-0 TP0[23:16] R/W 0h Upper eight bits of test pattern 0

8.2.6 Register 16h (offset = 16h) [reset = 0h]

Figure 8-25 Register 16h
15 14 13 12 11 10 9 8
TP1[23:8]
R/W-0h
7 6 5 4 3 2 1 0
TP1[23:8]
R/W-0h
Figure 8-26 Register 16h Field Descriptions
Bit Field Type Reset Description
15-0 TP1[23:8] R/W 0h Upper 16 bits of test pattern 1

8.2.7 Register 1Ch (offset = 1Ch) [reset = 0h]

Figure 8-27 Register 1Ch
15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
USER_BITS
R/W-0h
Figure 8-28 Register 1Ch Field Descriptions
Bit Field Type Reset Description
15-8 RESERVED R/W 0h Reserved. Do not change from the default reset value.
7-0 USER_BITS R/W 0h User-defined bits appended to the ADC conversion result.

8.2.8 Register 33h (offset = 33h) [reset = 0h]

Figure 8-29 Register 33h
15 14 13 12 11 10 9 8
RESERVED GE_CAL_EN3 RESERVED
R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED GE_CAL_EN2 RESERVED
R/W-0h R/W-0h R/W-0h
Figure 8-30 Register 33h Field Descriptions
Bit Field Type Reset Description
15-14 RESERVED R/W 0h Reserved. Do not change from the default reset value.
13 GE_CAL_EN3 R/W 0h Global control for gain error calibration.
0 : Gain error calibration disabled for all channels
1 : Gain error calibration enabled for all channels
12-7 RESERVED R/W 0h Reserved. Do not change from the default reset value.
6 GE_CAL_EN2 R/W 0h Global control for gain error calibration.
0 : Gain error calibration disabled for all channels
1 : Gain error calibration enabled for all channels
5-0 RESERVED R/W 0h Reserved. Do not change from the default reset value.

8.2.9 Register 34h (offset = 34h) [reset = 0h]

Figure 8-31 Register 34h
15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
RESERVED LAT_EN RESERVED
R/W-0h R/W-0h R/W-0h
Figure 8-32 Register 34h Field Descriptions
Bit Field Type Reset Description
15-5 RESERVED R/W 0h Reserved. Do not change from the default reset value.
4 LAT_EN R/W 0h For the ADS9119, set this field to 11b for optimum INL performance.
3-0 RESERVED R/W 0h Reserved. Do not change from the default reset value.

8.2.10 Register 90h (offset = 90h) [reset = 0h]

Figure 8-33 Register 90h
15 14 13 12 11 10 9 8
RESERVED TS_LD RESERVED
R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED
R/W-0h
Figure 8-34 Register 90h Field Descriptions
Bit Field Type Reset Description
15 RESERVED R/W 0h Reserved. Do not change from the default reset value.
14 TS_LD R/W 0h Trigger to load the temperature sensor output in address 0x91. Transition from 0 to 1 if this bit triggers the data load operation.
13-0 RESERVED R/W 0h Reserved. Do not change from the default reset value.

8.2.11 Register 91h (offset = 91h) [reset = 00h]

Figure 8-35 Register 91h
15 14 13 12 11 10 9 8
RESERVED TEMPERATURE_SENSOR
R/W-0h R/W-0h
7 6 5 4 3 2 1 0
TEMPERATURE_SENSOR
R/W-0h
Figure 8-36 Register 91h Field Descriptions
Bit Field Type Reset Description
15-10 RESERVED R/W 0h Reserved. Do not change from the default reset value.
9-0 TEMPERATURE_SENSOR R/W 0h 10-bit temperature sensor output. See the Temperature Sensor section.

8.2.12 Register C0h (offset = C0h) [reset = 0h]

Figure 8-37 Register C0h
15 14 13 12 11 10 9 8
RESERVED CLK1 OSR_INIT1 OSR_CLK
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
OSR_CLK RESERVED PD_CH
R/W-0h R/W-0h R/W-0h
Figure 8-38 Register C0h Field Descriptions
Bit Field Type Reset Description
15-13 RESERVED R/W 0h Reserved. Do not change from the default reset value.
12 CLK1 R/W 0h Selects the clock configuration based on output data lanes.
0 : Configuration for DATA_LANES = 0 or 2
1 : Not recommended
11-10 OSR_INIT1 R/W 0h Initialization for data averaging.
0 : Configuration for disabling data averaging
1 : Configuration for enabling data averaging
9-7 OSR_CLK R/W 0h Data output clock configuration for data averaging. See Table 7-3 for more details.
6-2 RESERVED R/W 0h Reserved. Do not change from the default reset value.
1-0 PD_CH R/W 0h Power-down control for the analog input channels.
0 : Normal operation
1 : ADC powered down
2 : No effect
3 : ADC powered down

8.2.13 Register C1h (offset = C1h) [reset = 0h]

Figure 8-39 Register C1h
15 14 13 12 11 10 9 8
RESERVED PD_REF RESERVED DATA_RATE
R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED CLK2
R/W-0h R/W-0h
Figure 8-40 Register C1h Field Descriptions
Bit Field Type Reset Description
15-12 RESERVED R/W 0h Reserved. Do not change from the default reset value.
11 PD_REF R/W 0h ADC reference voltage source selection.
0 : Internal reference enabled.
1 : Internal reference disabled. Connect the external reference voltage to the REFIO pin.
10-9 RESERVED R/W 0h Reserved. Do not change from the default reset value.
8 DATA_RATE R/W 0h Select data rate for the data interface.
0 : Double data rate (DDR)
1 : Single data rate (SDR)
7-1 RESERVED R/W 0h Reserved. Do not change from the default reset value.
0 CLK2 R/W 0h Select data rate for the data interface.
0 : Configuration for DATA_LANES = 2 or 7

8.2.14 Register C4h (offset = C4h) [reset = 0h]

Figure 8-41 Register C4h
15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
RESERVED OSR_INIT2 RESERVED OSR_INIT3 PD_CHIP
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
Figure 8-42 Register C4h Field Descriptions
Bit Field Type Reset Description
15-6 RESERVED R/W 0h Reserved. Do not change from the default reset value.
5-4 OSR_INIT2 R/W 0h Initialization for data averaging.
0 : Configuration for disabling data averaging
2 : Configuration for enabling data averaging
3-2 RESERVED R/W 0h Reserved. Do not change from the default reset value.
1 OSR_INIT3 R/W 0h Initialization for data averaging.
0 : Configuration for disabling data averaging
1 : Configuration for enabling data averaging
0 PD_CHIP R/W 0h Full chip power-down control.
0 : Normal device operation
1 : Full device powered down

8.2.15 Register C5h (offset = C5h) [reset = 0h]

Figure 8-43 Register C5h
15 14 13 12 11 10 9 8
RESERVED HI_FREQ_EN RESERVED CLK3 RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED RD_CLK RESERVED CLK4 RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
Figure 8-44 Register C5h Field Descriptions
Bit Field Type Reset Description
15-14 RESERVED R/W 0h Reserved. Do not change from the default reset value.
13 HI_FREQ_EN R/W 0h Fast analog input slew rate enable.
0: Normal slew rate,
1: Fast analog input control enabled. Recommended for input frequencies >2MHz. Also see the HI_FREQ register bit.
12-10 RESERVED R/W 0h Reserved. Do not change from the default reset value.
9 CLK3 R/W 0h Select data rate for the data interface.
0 : Configuration for DATA_LANES = 0 or 2
8 - 7 RESERVED R/W 0h Reserved. Do not change from the default reset value.
6-5 RD_CLK R/W 0h Data output clock control for data averaging. See the Data Averaging section for more details.
4 RESERVED R/W 0h Reserved. Do not change from the default reset value.
3 - 2 CLK4 R/W 0h Clock configuration for ADS9117. See the Data Interface section for details. Not applicable for the ADS9119 and ADS9118.
0 : 24-bit mode
3 : All other modes
1 - 0 RESERVED R/W 0h Reserved. Do not change from the default reset value.

8.2.16 Register FBh (offset = FBh) [reset = 0h]

Figure 8-45 Register FBh
15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
RESERVED NCO_SYSREF XOR_MODE CLK5 MIXER_EN
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
Figure 8-46 Register FBh Field Descriptions
Bit Field Type Reset Description
15-4 RESERVED R/W 0h Reserved. Do not change from the default reset value.
3 NCO_SYSREF R/W 0h Set to 1b when applying periodic pulses on the SMPL_SYNC pin.
0: Synchronize the NCO with one pulse on the SMPL_SYNC pin.
1: Synchronize the NCO with the first pulse on the SMPL_SYNC pin when using periodic pulses.
2 XOR_MODE R/W 0h Selects the bit with which the ADC output data is XORed when XOR output mode is enabled.
0 : The PRBS bit is output after the ADC LSB. ADC output data are XORed with the PRBS bit.
1 : ADC output data are XORed with the LSB of the conversion result.
1 CLK5 R/W 0h Clock configuration for the ADS9119 and ADS9118. See the Data Interface section for details. Not applicable for the ADS9117.
0 : 24-bit SDR and DDR modes
1 : Not recommended
0 MIXER_EN R/W 0h 0: Digital down converter disabled
1: Digital down converter enabled

8.2.17 Register FCh (offset = FCh) [reset = 0h]

Figure 8-47 Register FCh
15 14 13 12 11 10 9 8
NCO_PHASE_COUNT
R/W-0h
7 6 5 4 3 2 1 0
NCO_PHASE_COUNT
R/W-0h
Figure 8-48 Register FCh Field Descriptions
Bit Field Type Reset Description
15-0 NCO_PHASE_COUNT[15:0] R/W 0h Lower 15 bits of the NCO phase count. See the Digital Down Converter section.

8.2.18 Register FDh (offset = FDh) [reset = 0h]

Figure 8-49 Register FDh
15 14 13 12 11 10 9 8
NCO_FREQUENCY
R/W-0h
7 6 5 4 3 2 1 0
NCO_PHASE_COUNT
R/W-0h
Figure 8-50 Register FDh Field Descriptions
Bit Field Type Reset Description
15-8 NCO_FREQUENCY[7:0] R/W 0h Lower eight bits of the NCO phase count. See the Digital Down Converter section.
7-0 NCO_PHASE_COUNT[23:16] R/W 0h Upper eight bits of the NCO phase count. See the Digital Down Converter section.

8.2.19 Register FEh (offset = FEh) [reset = 0h]

Figure 8-51 Register FEh
15 14 13 12 11 10 9 8
NCO_FREQUENCY
R/W-0h
7 6 5 4 3 2 1 0
NCO_FREQUENCY
R/W-0h
Figure 8-52 Register FEh Field Descriptions
Bit Field Type Reset Description
15-0 NCO_FREQUENCY R/W 0h Upper 16 bits of the NCO phase count. See the Digital Down Converter section.