SLVSIO1B March 2026 – April 2026 UCG28836 , UCG28846
PRODUCTION DATA
| PIN | TYPE(1) | DESCRIPTION | ||
|---|---|---|---|---|
| NAME | QFN NO. | SOIC NO. | ||
| HV | 1 | 1 | P | HV startup, AC line input presence detection and X-cap discharge. |
| SW | 2 | 3 | P | Drain pin of integrated high-voltage GaN HEMT. This is also the sensing pin for valley switching and protections. |
| GND | 3, 10 | 5, 12 | G | Signal ground. Internally connected to power ground. |
| FLT | 4 | 6 | O | Fault pin for external overtemperature protection. Connect an NTC from this pin to GND. |
| FB | 5 | 7 | I | Feedback signal. Connect this pin to the collector of an optocoupler. |
| TR | 6 | 8 | I | Turns ratio setting. A resistor from this pin to GND sets the transformer turns ratio Np/Ns. |
| IPS | 7 | 9 | I | Peak current, and switch node slew rate setting pin. A resistor from this pin to GND sets the maximum and minimum primary-side peak current, and switch node voltage slew rate. |
| FCL | 8 | 10 | I | Switching frequency clamp and fault behavior setting. |
| CFX | 9 | 11 | I | Multifunction pin to enable/disable CCM mode, frequency foldback threshold setting and X-cap discharge enable and disable. |
| VCC | 11 | 13 | P | IC bias supply. Connect an external capacitor (at least 10V rated) from this pin to GND. The capacitor value can be between 15µF to 47µF. The capacitor value is determined by the hold up time for missing input line cycles. |
| GND | 12 | 14, 15, 16 | G | Power ground. Connect to negative terminal of input bulk capacitor. Add a ground plane with sufficient copper area below the thermal pad for efficient heat conduction to the PCB. |
| NC | 2, 4 | No connection for high voltage spacing. Do not connect any trace to these pins. | ||