SLVSIV2 August   2026 TPS7A14-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Excellent Transient Response
      2. 6.3.2 Global Undervoltage Lockout (UVLO)
      3. 6.3.3 Enable Input
      4. 6.3.4 Internal Foldback Current Limit
      5. 6.3.5 Active Discharge
      6. 6.3.6 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
      2. 6.4.2 Dropout Operation
      3. 6.4.3 Disable Mode
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1  Recommended Capacitor Types
      2. 7.1.2  Input, Output, and Bias Capacitor Requirements
      3. 7.1.3  Dropout Voltage
      4. 7.1.4  Behavior During Transition From Dropout Into Regulation
      5. 7.1.5  Device Enable Sequencing Requirement
      6. 7.1.6  Load Transient Response
      7. 7.1.7  Undervoltage Lockout Circuit Operation
      8. 7.1.8  Power Dissipation (PD)
      9. 7.1.9  Estimating Junction Temperature
      10. 7.1.10 Recommended Area for Continuous Operation
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Examples
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 Evaluation Module
      2. 8.1.2 Device Nomenclature
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

7.1.7 Undervoltage Lockout Circuit Operation

The VIN UVLO circuit makes sure that the regulator remains disabled when the input supply voltage is below the minimum operational voltage range, and makes sure that the regulator shuts down when the input supply collapses. Similarly, the VBIAS UVLO circuit makes sure that the regulator remains disabled when the bias supply voltage is less than the minimum operational voltage range, and makes sure that the regulator shuts down when the bias supply collapses.

Figure 7-2 shows the UVLO circuit response to various input or bias voltage events. The diagram can be separated into the following parts:

  • Region A: The output remains off while the input or bias voltage is below the UVLO rising threshold
  • Region B: Normal operation, regulating device
  • Region C: Brownout event above the UVLO falling threshold (UVLO rising threshold – UVLO hysteresis). The output can possibly fall out of regulation but the device remains enabled.
  • Region D: Normal operation, regulating device
  • Region E: Brownout event below the UVLO falling threshold. The device is disabled in most cases and the output falls as a result of the load and active discharge circuit. The device is re-enabled when the UVLO rising threshold is reached and a normal start up follows.
  • Region F: Normal operation followed by the input or bias falling to the UVLO falling threshold
  • Region G: The device is disabled when the input or bias voltages fall below the UVLO falling threshold to 0V. The output falls as a result of the load and active discharge circuit.
TPS7A14-Q1 Typical VIN or VBIAS UVLO Circuit OperationFigure 7-2 Typical VIN or VBIAS UVLO Circuit Operation