SLVSJ10 December   2025 MC111

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings Comm
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 I2C Timing Requirements
    7. 5.7 Timing Diagrams
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Motor Control
        1. 6.3.1.1 Duty Input
        2. 6.3.1.2 Duty Curve
        3. 6.3.1.3 Motor Start, Speed Change, and Stop
        4. 6.3.1.4 Open-Loop (Duty Cycle) Control
        5. 6.3.1.5 Closed-Loop (Speed) Control
        6. 6.3.1.6 Commutation
          1. 6.3.1.6.1 Hall Sensor
            1. 6.3.1.6.1.1 Field Direction Definition
            2. 6.3.1.6.1.2 Internal Hall Latch Sensor Output
          2. 6.3.1.6.2 Hall Offset
          3. 6.3.1.6.3 Square Commutation
          4. 6.3.1.6.4 Soft Commutation
        7. 6.3.1.7 PWM Modulation Modes
      2. 6.3.2 Protections
        1. 6.3.2.1 Locked Rotor Protection
        2. 6.3.2.2 Current Limit
        3. 6.3.2.3 Overcurrent Protection (OCP)
        4. 6.3.2.4 VM Undervoltage Lockout (UVLO)
        5. 6.3.2.5 VM Over Voltage Protection (OVP)
        6. 6.3.2.6 Thermal Shutdown (TSD)
        7. 6.3.2.7 Integrated Supply (VM) Clamp
    4. 6.4 Device Functional Modes
      1. 6.4.1 Active Mode
      2. 6.4.2 Sleep and Standby Mode
      3. 6.4.3 Fault Mode
      4. 6.4.4 Test Mode and One-Time Programmable Memory
    5. 6.5 Programming
      1. 6.5.1 I2C Communication
        1. 6.5.1.1 I2C Read
        2. 6.5.1.2 I2C Write
  8. 7 Register Map
    1. 7.1 USR_OTP Registers
    2. 7.2 USR_TM Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 External Components
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Bulk Capacitance
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History

7.1 USR_OTP Registers

Table 7-1 lists the memory-mapped registers for the USR_OTP registers. All register offset addresses not listed in Table 7-1 should be considered as reserved locations and the register contents should not be modified.

Table 7-1 USR_OTP Registers
Offset Acronym Register Name Section
0h INTERFACE_CONFIG0 Interface Configuration Register 0 Section 7.1.1
1h INTERFACE_CONFIG1 Interface Configuration Register 1 Section 7.1.2
2h START_STOP_CONFIG Start and Stop Configuration Register Section 7.1.3
3h DIN0 DIN0 Setting Section 7.1.4
4h DOUT0 DOUT0 Setting Section 7.1.5
5h DOUT1 DOUT1 Setting Section 7.1.6
6h DOUT2 DOUT2 Setting Section 7.1.7
7h DOUT3 DOUT3 Setting Section 7.1.8
8h DOUT4 DOUT4 Setting Section 7.1.9
9h DOUT5 DOUT5 Setting Section 7.1.10
Ah DOUT6 DOUT6 Setting Section 7.1.11
Bh DOUT7 DOUT7 Setting Section 7.1.12
Ch DOUT8 DOUT8 Setting Section 7.1.13
Dh HALL_TIME_CONFIG Configuration Register for Hall Offset Time Section 7.1.14
Eh COMMUTATION_CONFIG0 Commutation Configuration Register 0 Section 7.1.15
Fh COMMUTATION_CONFIG1 Commutation Configuration Register 1 Section 7.1.16
10h COMMUTATION_CONFIG2 Commutation Configuration Register 2 Section 7.1.17
11h COMMUTATION_CONFIG3 Commutation Configuration Register 3 Section 7.1.18
12h PROTECTION_CONFIG0 Configuration Register for Protection Settings Section 7.1.19
13h CLOSED_LOOP_CONFIG0 Least Significant byte of MAX_SPEED Section 7.1.20
14h CLOSED_LOOP_CONFIG1 KI_RATIO and MSN of MAX_SPEED in closed loop and DOUT_MAX in Open loop Section 7.1.21
15h CLOSED_LOOP_CONFIG2 KP_RATIO in closed loop and LRD settings Section 7.1.22
16h PROTECTION_CONFIG1 Register for Protections and PWM Dithering Section 7.1.23
17h GENERAL_CONFIG1 Register for ILIM_SEL, Hall and LRD settings Section 7.1.24
18h GENERAL_CONFIG2 Register for VM clamp, Prestart ramp and Hall Settings Section 7.1.25
19h GENERAL_CONFIG3 Register for Silence, Pole pair, LRD settings Section 7.1.26
1Ah GENERAL_CONFIG4 Configuration Register for DEMAG and Silence settings Section 7.1.27
1Bh USR_OTP_CRC Register for CRC calculated over USR_OTP Section 7.1.28

Complex bit access types are encoded to fit into small table cells. Table 7-2 shows the codes that are used for access types in this section.

Table 7-2 USR_OTP Access Type Codes
Access Type Code Description
Read Type
R R Read
Write Type
W W Write
Reset or Default Value
-n Value after reset or the default value

7.1.1 INTERFACE_CONFIG0 Register (Offset = 0h) [Reset = 00h]

INTERFACE_CONFIG0 is shown in Table 7-3.

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Table 7-3 INTERFACE_CONFIG0 Register Field Descriptions
Bit Field Type Reset Description
7 HALL_DEGLITCH_EN R/W 0h Enables HALL signal from HALL sensor to be deglitched for
  • 0h = HALL deglitch disabled
  • 1h = HALL deglitch enabled
6 PWM_IN_RANGE R/W 0h Selects the input PWM signal frequency detection range
  • 0h = 80Hz to 90kHz
  • 1h = 20Hz to 22kHz
5 PWM_OUT_FREQ R/W 0h Selects the PWM switching Frequency on the OUTx
  • 0h = Output PWM freq is 25kHz
  • 1h = Output PWM freq is 50kHz
4-3 ILIM_BLANK_SEL R/W 0h Selects additional blanking time for current limit (ILIM) on top of deadtime and default blanking
  • 0h = No additional blanking
  • 1h = 160ns (nominal) additional blanking
  • 2h = 320ns additional iLim blanking
  • 3h = 640ns additional iLim blanking
2 ILIM_DEGLITCH_SEL R/W 0h Selects the deglitch time for cycle by cycle current limit (ILIMIT).
  • 0h = deglitch time between 481ns to 732ns
  • 1h = deglitch time between 925ns to 1.419us
1-0 UVLO_SEL R/W 0h Selects the threshold at which UVLO gets triggered
  • 0h = Rising threshold 3V and falling threshold 2.7V
  • 1h = Rising threshold 4.2V and falling threshold 2.7V
  • 2h = Rising threshold 5.7V and falling threshold 2.7V
  • 3h = Rising threshold 7.6V and falling threshold 2.7V

7.1.2 INTERFACE_CONFIG1 Register (Offset = 1h) [Reset = 60h]

INTERFACE_CONFIG1 is shown in Table 7-4.

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Table 7-4 INTERFACE_CONFIG1 Register Field Descriptions
Bit Field Type Reset Description
7-6 DIN_HYS R/W 1h Selects duty cycle hysteresis DIN_HYS for speed curve.
  • 0h = 0%, no hysteresis
  • 1h = 1.2%
  • 2h = 2.4%
  • 3h = 4.8%
5 STBY_EN R/W 1h Selects OUTx behavior at DIN = 0%.
  • 0h = The driver commutates the motor at the DOUT0 duty cycle.
  • 1h = The driver disables the outputs after tSLEEP, but all internal circuitry remains active for faster re-enable.
4 SLEEP_EN R/W 0h Enables sleep mode when DIN = 0%.
  • 0h = Sleep mode is disabled. The driver state is determined by the STBY_EN bit.
  • 1h = Sleep mode is enabled. DOUT ramps down to 0% output duty cycle, and the driver goes into a low-power sleep mode after receiving no Hall edge for tSLEEP.
3 PWMDC_MODE R/W 0h Selects input mode between PWM or analog.
  • 0h = The PWM pin accepts a logic PWM duty cycle to control speed.
  • 1h = The PWM pin accepts and analog voltage to control motor speed.
2 FGRD_INVERT R/W 0h Selects FG/RD pin logic level during rotor lock or device fault.
  • 0h = FG/RD pin asserted low during rotor lock or device fault.
  • 1h = FG/RD pin asserted high during rotor lock or device fault.
1 FGRD_MODE R/W 0h Selects functionality of FG/RD pin.
  • 0h = FG speed feedback output
  • 1h = RD rotor lock detection feedback output
0 FGRD_FAULT_SEL R/W 0h Selects whether FG/RD pin reports device faults.
  • 0h = FG/RD pin reports rotor lock faults only
  • 1h = FG/RD reports rotor lock, overvoltage, overcurrent, thermal shutdown, and undervoltage fault conditions

7.1.3 START_STOP_CONFIG Register (Offset = 2h) [Reset = 89h]

START_STOP_CONFIG is shown in Table 7-5.

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Table 7-5 START_STOP_CONFIG Register Field Descriptions
Bit Field Type Reset Description
7 RAMP_ON_STOP_DIS R/W 1h Selects whether to ramp duty cycle down to zero while stopping or immediately apply zero duty cycle
  • 0h = Ramp duty cycle down to zero based based on PWM_RAMP_EN, PWM_RAMP_SEL and PWM_DECEL_SEL bits
  • 1h = Immediately Set FETs to HiZ when motor stop command is received
6-5 DINOFF R/W 0h Selects threshold of input DC above which output duty cycle will be zero
  • 0h = disabled, no value of input dyty cycle above which DOUT will be 0
  • 1h = When input duty cycle ≥ 90% DOUT will be mapped to 0%
  • 2h = When input duty cycle ≥ 95% DOUT will be mapped to 0%
  • 3h = When input duty cycle equals 100% DOUT will be mapped to 0%
4-2 DOUT_MIN R/W 2h Selects minimum value DOUT will be clamped to, if input duty cycle is between DIN0 and DINOFF
  • 0h = 0%
  • 1h = 5%
  • 2h = 10%
  • 3h = 12.5%
  • 4h = 15%
  • 5h = 20%
  • 6h = 25%
  • 7h = 30%
1-0 DOUT_START R/W 1h Selects DOUT to be applied when motor starts up. DOUT will be ramped to target duty cycle from this initial value.
  • 0h = 12.5% of DOUT_MAX in Open Loop and 12.5% in Closed Loop
  • 1h = 25% of DOUT_MAX in Open Loop and 25% in Closed Loop
  • 2h = 50% of DOUT_MAX in Open Loop and 50% in Closed Loop
  • 3h = 100% of DOUT_MAX in Open Loop and 100% in Closed Loop

7.1.4 DIN0 Register (Offset = 3h) [Reset = 16h]

DIN0 is shown in Table 7-6.

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Table 7-6 DIN0 Register Field Descriptions
Bit Field Type Reset Description
7-0 DIN0 R/W 16h Sets the minimum input duty cycle DIN, that the speed curve accepts.
DIN = 100%*DIN0/255
  • 0h = 0%
  • 1h = 0.39126%
  • 16h = 8.8% (default)
  • FFh = 100%

7.1.5 DOUT0 Register (Offset = 4h) [Reset = 1Ah]

DOUT0 is shown in Table 7-7.

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Table 7-7 DOUT0 Register Field Descriptions
Bit Field Type Reset Description
7-0 DOUT0 R/W 1Ah Sets the output duty DOUT when DIN ≤ DIN0
DOUT = 100%*DOUT0/255
  • 0h = 0%, all FETs off, putting the driver in a HiZ state
  • 1h = 0.39126%
  • 1Ah = 10.2% (default)
  • FFh = 100%

7.1.6 DOUT1 Register (Offset = 5h) [Reset = 20h]

DOUT1 is shown in Table 7-8.

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Table 7-8 DOUT1 Register Field Descriptions
Bit Field Type Reset Description
7-0 DOUT1 R/W 20h Sets the output duty DOUT when DIN = 12.5%
DOUT = 100%*DOUT1/255
  • 0h = 0%, both outputs remain low, putting the driver in a brake state
  • 20h = 12.5% (default)
  • FFh = 100%

7.1.7 DOUT2 Register (Offset = 6h) [Reset = 40h]

DOUT2 is shown in Table 7-9.

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Table 7-9 DOUT2 Register Field Descriptions
Bit Field Type Reset Description
7-0 DOUT2 R/W 40h Sets the output duty DOUT when DIN = 25%
DOUT = 100%*DOUT1/255
  • 0h = 0%, both outputs remain low, putting the driver in a brake state
  • 40h = 25% (default)
  • FFh = 100%

7.1.8 DOUT3 Register (Offset = 7h) [Reset = 60h]

DOUT3 is shown in Table 7-10.

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Table 7-10 DOUT3 Register Field Descriptions
Bit Field Type Reset Description
7-0 DOUT3 R/W 60h Sets the output duty DOUT when DIN = 37.5%
DOUT = 100%*DOUT1/255
  • 0h = 0%, both outputs remain low, putting the driver in a brake state
  • 60h = 37.5% (default)
  • FFh = 100%

7.1.9 DOUT4 Register (Offset = 8h) [Reset = 80h]

DOUT4 is shown in Table 7-11.

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Table 7-11 DOUT4 Register Field Descriptions
Bit Field Type Reset Description
7-0 DOUT4 R/W 80h Sets the output duty DOUT when DIN = 50%
DOUT = 100%*DOUT1/255
  • 0h = 0%, both outputs remain low, putting the driver in a brake state
  • 80h = 50% (default)
  • FFh = 100%

7.1.10 DOUT5 Register (Offset = 9h) [Reset = A0h]

DOUT5 is shown in Table 7-12.

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Table 7-12 DOUT5 Register Field Descriptions
Bit Field Type Reset Description
7-0 DOUT5 R/W A0h Sets the output duty DOUT when DIN = 62.5%
DOUT = 100%*DOUT1/255
  • 0h = 0%, both outputs remain low, putting the driver in a brake state
  • A0h = 62.5% (default)
  • FFh = 100%

7.1.11 DOUT6 Register (Offset = Ah) [Reset = C0h]

DOUT6 is shown in Table 7-13.

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Table 7-13 DOUT6 Register Field Descriptions
Bit Field Type Reset Description
7-0 DOUT6 R/W C0h Sets the output duty DOUT when DIN = 75%
DOUT = 100%*DOUT1/255
  • 0h = 0%, both outputs remain low, putting the driver in a brake state
  • C0h = 75% (default)
  • FFh = 100%

7.1.12 DOUT7 Register (Offset = Bh) [Reset = E0h]

DOUT7 is shown in Table 7-14.

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Table 7-14 DOUT7 Register Field Descriptions
Bit Field Type Reset Description
7-0 DOUT7 R/W E0h Sets the output duty DOUT when DIN = 87.5%
DOUT = 100%*DOUT1/255
  • 0h = 0%, both outputs remain low, putting the driver in a brake state
  • E0h = 87.5% (default)
  • FFh = 100%

7.1.13 DOUT8 Register (Offset = Ch) [Reset = FFh]

DOUT8 is shown in Table 7-15.

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Table 7-15 DOUT8 Register Field Descriptions
Bit Field Type Reset Description
7-0 DOUT8 R/W FFh Sets the output duty DOUT when DIN = 100%
DOUT = 100%*DOUT1/255
  • 0h = 0%, both outputs remain low, putting the driver in a brake state
  • FFh = 100% (default)

7.1.14 HALL_TIME_CONFIG Register (Offset = Dh) [Reset = 00h]

HALL_TIME_CONFIG is shown in Table 7-16.

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Table 7-16 HALL_TIME_CONFIG Register Field Descriptions
Bit Field Type Reset Description
7-0 HALL_OS_TIME R/W 0h Hall lead/lag time offset.
tHALL_OS = HALL_OS*10.24 us, 10.24 us/step
  • 00h = 0
  • 01h = 10.24us
  • 02h = 20.48us

7.1.15 COMMUTATION_CONFIG0 Register (Offset = Eh) [Reset = 00h]

COMMUTATION_CONFIG0 is shown in Table 7-17.

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Table 7-17 COMMUTATION_CONFIG0 Register Field Descriptions
Bit Field Type Reset Description
7-6 FG_MULTIPLIER R/W 0h This factor multiplies FG output frequency to keep speed feedback frequency the same when motor pole count changes.
  • 0h = 1/2x
  • 1h = 2/3x
  • 2h = 1x
  • 3h = 2x
5 FG_HALL_RAW_EN R/W 0h If this bit is high, then the FG_MULTIPLIER field is applied to the RAW_HALL signal instead of the HALL_OFFSET signal, to drive the FG_RD pin.
  • 0h = HALL_OFFSET signal drives FG_RD pin, based on FG_MULTIPLIER factor
  • 1h = HALL_RAW drives FG_RD pin, based on FG_MULTIPLIER factor. Note: 2/3x option is not valid for HALL_RAW signal.
4-3 COMMUTATION_MODE R/W 0h Selects commutation mode for output PWM waveshape.
  • 0h = Square commutation
  • 1h = Soft commutation
2-0 PWM_MODE R/W 0h Selects output behavior during OFF times for PWM, current limiting, and demagnetization
  • 0h = Asynchronous mode for PWM, current limiting, and demagnetization
  • 1h = Asynchronous mode for PWM and current limiting; Synchronous mode for demagnetization
  • 2h = Synchronous mode for PWM and current limiting; Asynchronous mode for demagnetization
  • 3h = Synchronous mode for PWM, current limiting, and demagnetization
  • 4h = Synchronous mode for PWM and current limiting; Hybrid mode for demagnetization
  • 5h = Asynchronous mode for PWM and current limiting; Hybrid mode for demagnetization
  • 6h = Hybrid mode for PWM and current limiting; Asynchronous mode for demagnetization
  • 7h = Hybrid mode for PWM, current limiting, and demagnetization

7.1.16 COMMUTATION_CONFIG1 Register (Offset = Fh) [Reset = A0h]

COMMUTATION_CONFIG1 is shown in Table 7-18.

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Table 7-18 COMMUTATION_CONFIG1 Register Field Descriptions
Bit Field Type Reset Description
7 PWM_RAMP_EN R/W 1h Enables PWM ramp function
  • 0h = PWM ramp function disabled, input duty cycle applied instantly to DOUT
  • 1h = PWM ramp function enabled, ramp rate set according to PWM_RAMP_SEL bits
6-5 PWM_RAMP_SEL R/W 1h The overall time from motor startup for DOUT to ramp from 0 to 100%. This also controls the ramp rate when increasing or decreasing input PWM duty cycle to change speed.
  • 0h = 10.4s (9.6%/s duty cycle ramp rate)
  • 1h = 5.2s (19.2%/s duty cycle ramp rate)
  • 2h = 2.6s (38.5%/s duty cycle ramp rate)
  • 3h = 1.3s (77%/s duty cycle ramp rate)
4-0 SRISE R/W 0h Sets the rising ramp for soft commutation. Default is 0 degrees for square commutation.
θSRISE = (SRISE*2.8 degrees)+2.8 degrees
  • 00h = 2.8 degrees
  • 01h = 5.6 degrees
  • 1Fh = 90 degrees

7.1.17 COMMUTATION_CONFIG2 Register (Offset = 10h) [Reset = 20h]

COMMUTATION_CONFIG2 is shown in Table 7-19.

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Table 7-19 COMMUTATION_CONFIG2 Register Field Descriptions
Bit Field Type Reset Description
7-6 RESERVED R/W 0h Reserved
5 PWM_DECEL_SEL R/W 1h Selects whetehr the ramp rate during deceleration is same as PWM_RAMP_SEL setting or half of that
  • 0h = Deceleration ramp rate set by PWM_RAMP_SEL
  • 1h = Deceleration ramp rate is half of PWM_RAMP_SEL
4-0 SFALL R/W 0h Sets the falling ramp for soft commutation. Default is 0 degrees for square commutation.
θSFALL = (SFALL*2.8 degrees)+2.8 degrees
  • 00h = 2.8 degrees
  • 01h = 5.6 degrees
  • 1Fh = 90 degrees

7.1.18 COMMUTATION_CONFIG3 Register (Offset = 11h) [Reset = 46h]

COMMUTATION_CONFIG3 is shown in Table 7-20.

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Table 7-20 COMMUTATION_CONFIG3 Register Field Descriptions
Bit Field Type Reset Description
7-6 AUTO_DEMAG_EN R/W 1h Selects fixed or automatic tDEMAG time
  • 0h = Sets tDEMAG according to DEMAG bits
  • 1h = Automatically determines duration of tDEMAG time by detecting the current zero crossing
  • 2h = Reserved
  • 3h = Reserved
5-4 AUTO_DEMAG_STEP R/W 0h Step resolution for Auto Demag
  • 0h = 2.56us
  • 1h = 5.12us
  • 2h = 10.24us
  • 3h = 20.48us
3 RESERVED R/W 0h Reserved
2-1 RESERVED R/W 0h Reserved
0 RESERVED R/W 0h Reserved

7.1.19 PROTECTION_CONFIG0 Register (Offset = 12h) [Reset = 04h]

PROTECTION_CONFIG0 is shown in Table 7-21.

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Table 7-21 PROTECTION_CONFIG0 Register Field Descriptions
Bit Field Type Reset Description
7 SPEED_LOOP_EN R/W 0h Enables or disables Closed Loop speed control operation
  • 0h = Open Loop operation with input command being target DutyCycle
  • 1h = Closed Loop operation with input command being target Speed
6 OVP_EN R/W 0h Enables or disables overvoltage protection
  • 0h = Overvoltage protection disabled
  • 1h = Overvoltage protection enabled
5-4 OVP_SEL R/W 0h Selects threshold past which OVP is asserted
  • 0h = Reserved
  • 1h = 22.6V rising and 21.1V falling
  • 2h = 18.1V rising and 16.6V falling
  • 3h = No OVP
3 OCP_RETRY_MODE R/W 0h Controls whether to retry indefinitely after OCP or stop after 3 consecutive retries
  • 0h = retry indefinitely
  • 1h = retry only 3 times consecutively
2-0 LRD_LONG_RETRY_SEL R/W 4h Selects multiplicatier to calculate tlock_long_retry from tLRD_START
  • 0h = x 2
  • 1h = x 4
  • 2h = x 8
  • 3h = x 10
  • 4h = x 12
  • 5h = x 16
  • 6h = x 24
  • 7h = x 28

7.1.20 CLOSED_LOOP_CONFIG0 Register (Offset = 13h) [Reset = 00h]

CLOSED_LOOP_CONFIG0 is shown in Table 7-22.

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Table 7-22 CLOSED_LOOP_CONFIG0 Register Field Descriptions
Bit Field Type Reset Description
7-0 MAX_SPEED_LSB R/W 0h Sets the 8 LSBs of the 12 bit value representing the maximum electrical speed in Hz device should target, when operating at 100% DutyCycle in Closed loop. Used for calculating the target speed based on the input Duty Cycle observed on the PWM pin as per the equation Target elecrical speed (Hz) = Input duty cycle * MAX_SPEED

7.1.21 CLOSED_LOOP_CONFIG1 Register (Offset = 14h) [Reset = FFh]

CLOSED_LOOP_CONFIG1 is shown in Table 7-23.

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Table 7-23 CLOSED_LOOP_CONFIG1 Register Field Descriptions
Bit Field Type Reset Description
7-4 DOUT_MAX_MSN OR KI_RATIO R/W Fh Open Loop: Sets the Most Significant Nibble of DOUT_MAX, the maximum value DOUT will be clamped to if DIN is between DIN0 and DINOFF. DOUT_MAX has a min clamp of 25% Closed Loop: Sets the 3 bits for KI_RATIO
  • 0h = Kp * 8
  • 1h = Kp * 4
  • 2h = Kp * 2
  • 3h = Kp * 1
  • 4h = Kp/2
  • 5h = Kp/4
  • 6h = Kp/8
  • 7h = Kp/16
3-0 DOUT_MAX_LSN OR MAX_SPEED_MSN R/W Fh Open Loop: Sets the Least Significant Nibble of DOUT_MAX, the maximum value DOUT will be clamped to if DIN is between DIN0 and DINOFF. DOUT_MAX has a min clamp of 25% Closed Loop: Sets the 4 MSBs of the 12 bit value representing the maximum electrical speed in Hz device should target, when operating at 100% DutyCycle in Closed loop. Used for calculating the target speed based on the input Duty Cycle observed on the PWM pin as per the equation Target elecrical speed (Hz) = Input duty cycle * MAX_SPEED

7.1.22 CLOSED_LOOP_CONFIG2 Register (Offset = 15h) [Reset = 02h]

CLOSED_LOOP_CONFIG2 is shown in Table 7-24.

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Table 7-24 CLOSED_LOOP_CONFIG2 Register Field Descriptions
Bit Field Type Reset Description
7-6 LRD_NRETRY_STARTUP R/W 0h Number of retries for very first start-up attempt after wakeup from reset or SLEEP or STBY, before enforcing a long retry period tlock_long_retry.
  • 0h = Just one retry attempt in first set of retry attempts
  • 1h = Two retry attempts in first set of retry attempts
  • 2h = Three retry attempts in first set of retry attempts
  • 3h = Four retry attempts in first set of retry attempts
5-4 LRD_NRETRY_RUN R/W 0h Number of retries for subsequent start-up attempts after first start-up attempt, post wakeup from reset or SLEEP or STBY, before enforcing a long retry period tlock_long_retry.
  • 0h = Just one retry attempt in subsequent set of retry attempts
  • 1h = Two retry attempts in subsequent set of retry attempts
  • 2h = Three retry attempts in subsequent set of retry attempts
  • 3h = Four retry attempts in subsequent set of retry attempts
3 DEADTIME_SEL R/W 0h Reduced deadtime duration from 600ns to 520ns
  • 0h = Deadtime is 600ns
  • 1h = Deadtime is 520ns
2-0 KP_RATIO R/W 2h Proportional component in the Closed Loop Speed Controller.
  • 0h = 8/fMax
  • 1h = 4/fMax
  • 2h = 2/fMax
  • 3h = 1/fMax
  • 4h = 1/(2*fMax)
  • 5h = 1/(4*fMax)
  • 6h = 1/(8*fMax)
  • 7h = 1/(16*fMax)

7.1.23 PROTECTION_CONFIG1 Register (Offset = 16h) [Reset = 44h]

PROTECTION_CONFIG1 is shown in Table 7-25.

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Table 7-25 PROTECTION_CONFIG1 Register Field Descriptions
Bit Field Type Reset Description
7 OVP_BLANK_SEL R/W 0h Selects the duration of blanking to be applied in during peak duty cycle phase.
  • 0h = Blanking active after 1ms
  • 1h = Blanking active after 4ms
6 OVP_BLANK_EN R/W 1h Enables or disables the OVP Blanking time duting the peak duty cycle phase
  • 0h = No OVP blanking in Peak duty cycle phase and blanking will only be active for SRISE and SFALL phases
  • 1h = OVP blanking in Peak duty cycle phase according to OVP_BLANK_SEL in addition to SRISE and SFALL phases
5 OCP_DEGLITCH_SEL R/W 0h Selects deglitch time for OCP
  • 0h = OCP deglitch time is 500ns
  • 1h = OCP deglitch time is 1us
4 RESERVED R/W 0h Reserved
3-2 RESERVED R/W 0h Reserved
1 RESERVED R/W 0h Reserved
0 DITHER_EN R/W 0h Enables dithering of internal oscillator and therefore output PWM when set high
  • 0h = Dithering disabled
  • 1h = Dithering enabled

7.1.24 GENERAL_CONFIG1 Register (Offset = 17h) [Reset = 46h]

GENERAL_CONFIG1 is shown in Table 7-26.

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Table 7-26 GENERAL_CONFIG1 Register Field Descriptions
Bit Field Type Reset Description
7 HALL_INVERT R/W 0h This bit inverts the Hall offset signal to the commutation block.
  • 0h = Non-inverted Hall latch signal
  • 1h = Inverted Hall latch signal
6 HALL_TIME_MODE R/W 1h Hall offset time lead/lag select bit
  • 0h = The Hall offset signal lags the Hall latch output signal by tHALL_OS
  • 1h = The Hall offset signal leads the Hall latch output signal by tHALL_OS
5-4 LRD_TIME_STARTUP R/W 0h Selects the locked rotor detection time tLRD_START at start-up. Also used to calculate tlock_long_retry from
  • 0h = 325ms
  • 1h = 440ms
  • Ah = 524ms
  • Bh = 1.05s
3-0 ILIMIT_SEL R/W 6h Selects the current limit threshold. Only values from 0h to 9h are valid.
  • 0h = 0.33 A
  • 1h = 0.44 A
  • 2h = 0.55 A
  • 3h = 0.66 A
  • 4h = 0.77 A
  • 5h = 0.88 A
  • 6h = 0.99 A
  • 7h = 1.10 A
  • 8h = 1.21 A
  • 9h = 1.32 A

7.1.25 GENERAL_CONFIG2 Register (Offset = 18h) [Reset = 81h]

GENERAL_CONFIG2 is shown in Table 7-27.

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Table 7-27 GENERAL_CONFIG2 Register Field Descriptions
Bit Field Type Reset Description
7 VM_CLAMP_DIS R/W 1h Disables the VM Clamp feature
  • 0h = VM Clamp enabled
  • 1h = VM Clamp disabled
6 HALL_ANGLE_MODE R/W 0h Selects whether the angle component of Hall Offset is to be applied in leading or lagging direction
  • 0h = The Hall offset signal leads the Hall latch output signal by θHALL_OS_ANGLE
  • 1h = The Hall offset signal lags the Hall latch output signal by θHALL_OS_ANGLE
5-1 HALL_OS_ANGLE R/W 0h The angle component of Hall Offset
  • 0h = 0 degrees
  • 1h = 1.4 degrees
  • 1Fh = 43.6 degrees
0 PRESTART_RAMP_EN R/W 1h Enables prestart PWM ramp function
  • 0h = Prestart ramp function disabled, input duty cycle applied instantly to DOUT
  • 1h = Prestart ramp function enabled, ramp rate set according to PWM_RAMP_SEL bits

7.1.26 GENERAL_CONFIG3 Register (Offset = 19h) [Reset = 24h]

GENERAL_CONFIG3 is shown in Table 7-28.

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Table 7-28 GENERAL_CONFIG3 Register Field Descriptions
Bit Field Type Reset Description
7-4 SILENCE_ANGLE R/W 2h Sets the angle duration for silence at beginning of commutation
  • 0h = 0.0
  • 1h = 1.4
  • 2h = 2.8
  • 3h = 4.2
  • 4h = 5.6
  • 5h = 7.0
  • 6h = 8.4
  • 7h = 9.8
  • 8h = 11.3
  • 9h = 12.7
  • 10h = 14.1
  • 11h = 15.5
  • 12h = 16.9
  • 13h = 18.3
  • 14h = 19.7
  • 15h = 21.1
3-2 POLE_PAIR R/W 1h Indicates number of pole pairs in the rotor
  • 0h = One pole pair
  • 1h = Two pole pairs
  • 2h = Three pole pairs
  • 3h = Four pole pairs
1 LRD_RETRY_DIS R/W 0h Disables retries after 5 consecutive attempts whrn locked rotor is detected
  • 0h = Infinite number of retries
  • 1h = Retries limited to 5
0 PWRUP_PWMDC_MASK R/W 0h Masks input speed command at the PWM pin for 1s during initial power up from reset condition
  • 0h = No masking at PWM pin input
  • 1h = Masks PWM pin input for 1s during initial power up enabled

7.1.27 GENERAL_CONFIG4 Register (Offset = 1Ah) [Reset = 08h]

GENERAL_CONFIG4 is shown in Table 7-29.

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Table 7-29 GENERAL_CONFIG4 Register Field Descriptions
Bit Field Type Reset Description
7-1 DEMAG_TIME R/W 4h Sets the DEMAG time
  • 0h = 0us
  • 1h = 10.24us
  • 2h = 20.48us
  • 3Fh = 645.12us
  • 7Fh = 1.29ms
0 SILENCE_MODE R/W 0h Selects the state of output FETs during silence phase
  • 0h = All FETs in HiZ during silence phase
  • 1h = Asyncronous mode in SILENCE phase

7.1.28 USR_OTP_CRC Register (Offset = 1Bh) [Reset = 00h]

USR_OTP_CRC is shown in Table 7-30.

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Table 7-30 USR_OTP_CRC Register Field Descriptions
Bit Field Type Reset Description
7-0 USR_OTP_CRC R/W 0h CRC value calculated over USR_OTP registers