SLVSJL5B August 2025 – June 2026 CC2755P20
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
|---|---|---|---|---|---|
| Input voltage range | 0 | VDDS | V | ||
| Clock frequency | 32 | KHz | |||
| Voltage divider accuracy | Input voltage range is between VDDS/4 and VDDS×3/4 | 97% | |||
| Offset | Measured at VDDS / 2 (Errors seen when using two external inputs ) | ±15 | mV | ||
| Decision time | Step from –50mV to 50mV | 1 | 3 | Clock Cycle | |
| Comparator enable time | COMP_LP disable →
enable, VIN+, VIN– from pins, Overdrive ≥ 20mV | 80 | µs | ||
| Current consumption | Including using VDDS/2 as internal reference at VIN– comparator terminal | 370 | nA |