SLVSJL5B August 2025 – June 2026 CC2755P20
PRODUCTION DATA
| PARAMETERS | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| fEXTCI | External clock input frequency | 24 | MHz | |||
| EXTCIDC | External clock input duty cycle | 40 | 60 | % | ||
| fMCLK | MCLK clock output frequency | 24 | MHz | |||
| MCLKDC | MCLK clock duty cycle | 46 | 52 | % | ||
| fSCLK | SCLK clock output frequency | VDDS = 1.71V | 3.27 | MHz | ||
| fSCLK | SCLK clock output frequency | VDDS = 3.8V | 6.145 | MHz | ||
| SCLKDC | SCLK clock duty cycle | 46 | 54 | % | ||
| tWS,valid | WS data output valid time (Falling edge of SCLK to WS data valid) | 42 | 49 | ns | ||
| tSDOUT,valid | SD data output valid time (Falling edge of SCLK to SD data valid) | 37 | 62 | ns | ||
| tSDIN,setup | SD data input setup time (before rising edge of SCLK) | 9 | ns | |||
| tSDIN,hold | SD data input hold time (after rising edge of SCLK) | 5 | ns | |||