SLVSJS0 December   2025 TMP4719-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Initialization and Default Temperature Conversion
      2. 7.3.2 Series Resistance Cancellation
      3. 7.3.3 ALERT and T_CRIT Output
      4. 7.3.4 1.2V Logic Compatible Inputs
      5. 7.3.5 Digital Filter
      6. 7.3.6 One-Shot Conversions
    4. 7.4 Device Functional Modes
      1. 7.4.1 Interrupt and Comparator Mode
        1. 7.4.1.1 Interrupt Mode
        2. 7.4.1.2 Comparator Mode
        3. 7.4.1.3 T_CRIT Output
      2. 7.4.2 Shutdown Mode
      3. 7.4.3 Continuous Conversion Mode
    5. 7.5 Programming
      1. 7.5.1 Temperature Data Format
      2. 7.5.2 I2C and SMBus Interface
      3. 7.5.3 Serial Bus Address
      4. 7.5.4 Bus Transactions
        1. 7.5.4.1 Writes
        2. 7.5.4.2 Reads
      5. 7.5.5 SMBus Alert Mode
  9. 8 Register Map
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

7.4.1.3 T_CRIT Output

The TMP4719-Q1 T_CRIT pin is an active-low, open-drain output which is asserted at the end of a conversion cycle when the measured temperature exceeds a T_CRIT Limit defined in the T_CRIT limit registers. A T_CRIT Status Register flag is set at the end of a conversion cycle when the measured temperature exceeds a T_CRIT Limit. The T_CRIT pin deasserts at the end of a conversion cycle if the temperature measurement is less than the T_CRIT limit – T_CRIT Hysteresis. The T_CRIT Hysteresis is set in the Hysteresis register.

When the TMP4719-Q1 is set in interrupt mode, the status register flag is cleared by reading the status register. The Status Register flag continues to set after the end of a conversion cycle until the temperature measurement is below the T_CRIT limit – T_CRIT Hysteresis value or the device is reset. T_CRIT has no mask bit. Note that reading the Status Register sets the ALERT mask bit of the Configuration Register if any flag in the Status Register, except the ADC_Busy flag and Remote Diode Fault flag, is set. The ALERT mask bit does not mask the T_CRIT pin, which means the clearance of ALERT mask bit has no influence on T_CRIT pin, and T_CRIT has no mask bit. There are separate T_CRIT Limit values and status register flags for the remote and local temperature measurements.

Figure 7-7 shows the behavior of the T_CRIT pin and flags in interrupt mode.

TMP4719-Q1 T_CRIT Output Timing Diagram-Interrupt ModeFigure 7-7 T_CRIT Output Timing Diagram-Interrupt Mode

When the TMP4719-Q1 is in comparator mode, the status register flag is only cleared at the end of a conversion cycle if the temperature measurement is below the T_CRIT limit – T_CRIT Hysteresis value. Figure 7-8 shows the behavior of the T_CRIT pin and flags in comparator mode.

TMP4719-Q1 T_CRIT Output Timing Diagram-Comparator ModeFigure 7-8 T_CRIT Output Timing Diagram-Comparator Mode