SLVSJS0 December   2025 TMP4719-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Initialization and Default Temperature Conversion
      2. 7.3.2 Series Resistance Cancellation
      3. 7.3.3 ALERT and T_CRIT Output
      4. 7.3.4 1.2V Logic Compatible Inputs
      5. 7.3.5 Digital Filter
      6. 7.3.6 One-Shot Conversions
    4. 7.4 Device Functional Modes
      1. 7.4.1 Interrupt and Comparator Mode
        1. 7.4.1.1 Interrupt Mode
        2. 7.4.1.2 Comparator Mode
        3. 7.4.1.3 T_CRIT Output
      2. 7.4.2 Shutdown Mode
      3. 7.4.3 Continuous Conversion Mode
    5. 7.5 Programming
      1. 7.5.1 Temperature Data Format
      2. 7.5.2 I2C and SMBus Interface
      3. 7.5.3 Serial Bus Address
      4. 7.5.4 Bus Transactions
        1. 7.5.4.1 Writes
        2. 7.5.4.2 Reads
      5. 7.5.5 SMBus Alert Mode
  9. 8 Register Map
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

6.6 I2C Interface Timing

minimum and maximum specifications are over –40 °C to 125 °C and VDD = 1.62 V to 5.5 V (unless otherwise noted)(1)
STANDARD MODE FAST MODE UNIT
MIN MAX MIN MAX
f(SCL) SCL operating frequency(2) 1 100 1 400 kHz
t(BUF) Bus free time between STOP and START condition 4.7 – 1.3 – µs
t(HDSTA) Hold time after repeated START condition. After this period, the first clock is generated. 4.0 – 0.6 – µs
t(SUSTA) Repeated START condition setup time 4.7 – 0.6 – µs
t(SUSTO) STOP condition setup time 4.0 – 0.6 – µs
t(HDDAT) Data hold time(3) 0 3450 0 900 ns
t(SUDAT) Data setup time 250 – 100 – ns
t(LOW) SCL clock LOW period 4.7 – 1.3 – µs
t(HIGH) SCL clock HIGH period 4.0 – 0.6 – µs
t(VDAT) Data valid time (data response time)(4) – 3.45 – 0.9 µs
tF Clock and data fall time(5) – 300 20 ×
(VDD / 5.5 V)		 300 ns
tR Clock and data rise time(5) – 1000 20 300 ns
ttimeout Timeout (SCL = GND) 20 30 20 30 ms
(1) The controller and target have the same I/O supply value. Values are based on statistical analysis of samples tested during initial release.
(2) Device is equipped with a 50-ns spike filter on both SCL and SDA lines. The filter allows the device to be used alongside I3C devices without impacting the communication.
(3) The maximum t(HDDAT) can be 3.45 µs and 0.9 µs for Standard Mode and Fast Mode, but must be less than the maximum of t(VDAT) by a transition time.
(4) t(VDAT) = time for data signal from SCL LOW to SDA output (HIGH to LOW, depending on which is worse).
(5) Device is not sensitive to rise and fall time. Violation of rise and fall time does not lead to communication failure.