SLVSLB8 May   2026 TLVM65030

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Descriptions
      1. 6.3.1 Output Voltage Selection
      2. 6.3.2 EN Pin and Use as VIN UVLO
      3. 6.3.3 Mode Selection
        1. 6.3.3.1 MODE/SYNC Pin Uses for Synchronization
        2. 6.3.3.2 Clock Locking
      4. 6.3.4 Adjustable Switching Frequency
      5. 6.3.5 Internal LDO, VCC UVLO, and BIAS Input
      6. 6.3.6 Bootstrap Voltage (BST Pin)
      7. 6.3.7 Soft Start and Recovery From Dropout
      8. 6.3.8 Monitoring Features
        1. 6.3.8.1 Power-Good Monitor
        2. 6.3.8.2 Overcurrent and Short-Circuit Protection
        3. 6.3.8.3 Hiccup
        4. 6.3.8.4 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown Mode
      2. 6.4.2 Active Mode
        1. 6.4.2.1 Peak Current Mode Operation
        2. 6.4.2.2 Auto Mode Operation
          1. 6.4.2.2.1 Diode Emulation
        3. 6.4.2.3 FPWM Mode Operation
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Custom Design With WEBENCH® Tools
        2. 7.2.2.2 Choosing the Switching Frequency
        3. 7.2.2.3 FB for Adjustable or Fixed Output Voltage Mode
        4. 7.2.2.4 Output Capacitor Selection
        5. 7.2.2.5 Input Capacitor Selection
        6. 7.2.2.6 CBOOT
        7. 7.2.2.7 External UVLO
        8. 7.2.2.8 Maximum Ambient Temperature
      3. 7.2.3 Application Curves
    3. 7.3 Best Design Practices
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
        1. 7.5.1.1 Ground and Thermal Considerations
      2. 7.5.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Third-Party Products Disclaimer
      2. 8.1.2 Development Support
        1. 8.1.2.1 Custom Design With WEBENCH® Tools
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

6.4.2.1 Peak Current Mode Operation

The following operating description of the TLVM65030 refers to Section 6.2 and the waveforms in Figure 6-9. Both supply a regulated output voltage by turning on the internal high-side (HS) and low-side (LS) NMOS switches with varying duty cycle (D). During the HS switch on-time, the SW terminal voltage, VSW, swings up to approximately VIN, and the inductor current, iL, increases with a linear slope. The HS switch is turned off by the control logic. During the HS switch off-time, tOFF, the LS switch is turned on. Inductor current discharges through the LS switch, forcing VSW to swing below ground by the voltage drop across the LS switch. The regulator loop adjusts the duty cycle to maintain a constant output voltage. D is defined by the on-time of the HS switch over the switching period: D = TON / (TON + TOFF).

In an ideal buck converter, where losses are ignored, D is proportional to the output voltage and inversely proportional to the input voltage: D = VOUT / VIN.

TLVM65030 SW Voltage and Inductor Current Waveforms in Continuous Conduction Mode (CCM)Figure 6-9 SW Voltage and Inductor Current Waveforms in Continuous Conduction Mode (CCM)

To get accurate DC load regulation, a voltage feedback loop is used. Peak and valley inductor currents are sensed for peak current mode control and current protection. The regulator operates with continuous conduction mode with constant switching frequency when load level is above one half of the minimum peak inductor current. The internally-compensated regulation network achieves fast and stable operation with small external components and low-ESR capacitors.