In this reference design, TLC555-Q1 is used to generate a pair of complementary PWM signal, of which the switching frequency can be self-adjustable. At lighter load the switching frequency is decreased to about 140kHz to reduce gate drive loss and switching loss, and at higher load the switching frequency is increased to resonance (about 300kHz) where switching loss can be even lower.

The output current of the SCC power stage is first sensed by the bidirectional current sense INA241-Q1 (not shown in Figure 2-3). Then the rail-to-rail amplifier TLV6001-Q1 creates an output voltage:

V_amp = 3.3V – I_LV_SNS (1)

Since for PNP transistor V_e – V_b = 0.6V, two equations for the PNP transistor Q1 on the left can be derived to associate the amplifier output with the bias current I_ec:

3.3V – 680Ω × I_ec = V_e (2)

(V_e – 0.6V) – 1kΩ × I_ec = V_amp (3)

Then the following equation can be derived:

V_amp = 2.7V – 1.68kΩ × I_ec (4)

Further combining with (1), the final relationship of I_LV_SNS and I_ec are:

I_LV_SNS = 0.6V + 1.68kΩ × I_ec (5)

(5) demonstrates that the higher the output current, the higher the bias current injecting into the charging and discharging circuit of TLC555-Q1 is, and hence higher output frequency.

Also note that due to the nature of the astable operation of TLC555-Q1, the duty ratio of the PWM output of TLC555-Q1 here is not 50%. Therefore, the current mirror section of this circuit is deliberately set to be twice the desired frequency (280kHz to 640kHz), and a following frequency divider by two using the D-latch can reduce the frequency by half (down to 140kHz to 320kHz) and also reset the duty ratio to 50%.

For further information on the astable operation of TLC555-Q1, read the datasheet for more detailed discussions.

Figure 2-3 PWM Generation Circuit