SLVT229 December   2025

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 High Side Gate Drive Circuit
      2. 2.2.2 PWM Generation Circuit
    3. 2.3 Highlighted Products
      1. 2.3.1 UCC21330-Q1 Overview
      2. 2.3.2 UCC27211A-Q1 Overview
      3. 2.3.3 TPS1212-Q1 Overview
  9. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
    2. 3.2 Test Setup
    3. 3.3 Test Results
      1. 3.3.1 Efficiency Data
      2. 3.3.2 Efficiency Graphs
      3. 3.3.3 Output Voltage Ripple
      4. 3.3.4 Thermal Images
      5. 3.3.5 Switch Voltage Stress of High Side Switches
      6. 3.3.6 Load Transients
      7. 3.3.7 Reverse Step-up Operation of SCC
  10. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 PCB Layout Recommendations
    2. 4.2 Documentation Support
    3.     Trademarks

UCC21330-Q1 Overview

The UCC21330-Q1 is an isolated dual channel gate driver family with programmable dead time and wide temperature range. The UCC21330-Q1 is designed with 4A peak-source and 6A peak-sink current to drive power MOSFET, SiC, GaN, and IGBT transistors.

The UCC21330-Q1 can be configured as two low-side drivers, two high-side drivers, or a half-bridge driver. The input side is isolated from the two output drivers by a 3kVRMS isolation barrier, with a minimum of 125V/ns common-mode transient immunity (CMTI).

Protection features include: resistor programmable dead time, disable feature to shut down both outputs simultaneously, and integrated de-glitch filter that rejects input transients shorter than 5ns. All supplies have UVLO protection.

Features:

  • Universal: dual low-side, dual high-side or half bridge driver
  • AEC-Q100 qualified with the following results
  • Device temperature grade 1
  • Junction temperature range –40 to +150°C
  • Up to 4A peak source and 6A peak sink output
  • Common-mode transient immunity (CMTI) greater than 125V/ns
  • Up to 25V VDD output drive supply
  • 5V, 8V, 12V VDD UVLO options
  • Switching parameters:
  • 33ns typical propagation delay
  • 5ns maximum pulse-width distortion
  • 10µs maximum VDD power-up delay
  • UVLO protection for all power supplies
  • Fast disable for power sequencing